Patents by Inventor Ronald L. Treadway

Ronald L. Treadway has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5015970
    Abstract: A PLL architecture is disclosed which incorporates a coarse adjustment feedback loop and a fine adjustment feedback loop together providing a combined error signal to a single VCO. The coarse adjustment feedback loop includes two digital counters set to divide the VCO output frequency by two different numbers. The outputs of the counters are coupled to the inputs of respective phase-frequency detectors, and the pump-up output of one of the detectors and the pump-down output of the other detector are used as the coarse adjustment pump-up and pump-down signals, respectively, in the coarse adjustment feedback loop. The coarse adjustment feedback loop thereby establishes a frequency range limitation for the fine adjustment feedback loop.
    Type: Grant
    Filed: February 15, 1990
    Date of Patent: May 14, 1991
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Bertrand J. Williams, Ronald L. Treadway
  • Patent number: 4905137
    Abstract: Page-mode-organized ROMs and associated circuitry are connected only to data and control buses in an information processing system. Addressing and reading of the ROMs are controlled by a processor without connecting the ROMs to an address bus. Selection of a particular ROM and of a particular page in the selected ROM is accomplished by applying a first control signal to the control bus and a first data word to the data bus. This first data word thus serves as the address of the selected page in the selected ROM. Then a particular byte of the selected page is selected by applying a second control signal to the control bus and a second data word to the data bus. This second data word serves as the address of the selected byte. Subsequently, in response to a third control signal, the selected byte is read out of the selected ROM and applied to the data bus.
    Type: Grant
    Filed: December 18, 1987
    Date of Patent: February 27, 1990
    Assignee: North American Philips Corporation Signetics Division
    Inventors: Gregory K. Goodhue, William J. Price, Ronald L. Treadway, Brian M. Willis
  • Patent number: 4101974
    Abstract: A programmable read-only memory circuit including a plurality of fusible link memory cells is disclosed in which a first auxiliary current source is employed to selectively isolate a cell location to be volatized during memory personalization and a second auxiliary current source is employed to volatize or personalize a fusable link in the selected memory cell for insuring complete volatilization of the fusible link.
    Type: Grant
    Filed: September 30, 1977
    Date of Patent: July 18, 1978
    Assignee: Motorola, Inc.
    Inventors: Dennis L. Immer, Michael S. Millhollan, Ronald L. Treadway
  • Patent number: 4027285
    Abstract: An N-bit binary address decoder suitable for use in an emitter-coupled logic bipolar random access memory (RAM) is provided. Each of the N address input signals is applied to an input terminal and is level shifted and applied to the input node of an emitter-coupled logic inverter. The outputs of the emitter-coupled logic inverter are the collectors of the emitter-coupled transistors on which complementary output signals representative of the corresponding binary address input signal are produced. The complementary output signals generated by the N inverters are connected to 2.sup.N AND gates to form the possible 2.sup.N minterm combinations. Each of the AND gates includes a load resistor coupled to a power supply and N Schottky diodes having their anodes coupled to the load resistor and their cathodes coupled to the corresponding address inverter output terminals.
    Type: Grant
    Filed: May 2, 1975
    Date of Patent: May 31, 1977
    Assignee: Motorola, Inc.
    Inventors: Michael S. Millhollan, Ronald L. Treadway
  • Patent number: 3973246
    Abstract: A bipolar sense-write circuit is provided for sensing voltage levels representative of a logical "1" or "0" stored in a flip-flop storage cell and for writing voltage levels into the flip-flop storage cell. The sense-write circuit includes first and second amplifier stages which, when coupled to a selected flip-flop storage cell produce a voltage in the amplifier section approximately equal to the voltage on a collector node in the flip-flop storage cell. Each amplifier stage of the sense-write circuit utilizes a side of the selected flip-flop storage cell as a part of that amplifier stage, if the corresponding side of the flip-flop storage cell is "on". The amplifier stage connected to the "on" side of the selected flip-flop storage cell acts as a unity gain amplifier, such that the row selection voltage appears at the output of that amplifier stage.
    Type: Grant
    Filed: July 11, 1975
    Date of Patent: August 3, 1976
    Assignee: Motorola, Inc.
    Inventors: Michael S. Millhollan, Ronald L. Treadway