Abstract: A read only memory is organized as a matrix of field effect transistors wherein logic levels are determined by the presence or absence of a gate which permits transistor action. The memory is addressed using a gate decode tree which selects the gates of a column of matrix devices and a source decode tree which selects the source lines of a row of matrix devices. Sensing of the logic level at a selected location is accomplished by a change of state output sense circuit which dynamically senses and provides a static output using a polarity hold circuit. Clamped, boot-strapped inverter circuits are provided in both input and output circuitry to maintain voltage, at selected internal nodes at a voltage intermediate predetermined minimum and maximum values.