Abstract: An improved content addressable memory includes a control circuit which, during a single clock pulse, receives and compares one search address on search address input terminals to compare addresses in N address registers, and simultaneously the control circuit conditionally writes a previously received search address into a selectable one of N address registers. With this improvement, the operating speed of the content addressable memory is increased since the writing of one search address into an address register and the searching with another search address does not require two separate clock cycles.