Abstract: The invention described herein is directed to different embodiments of a wireless communications device that can be used in many different applications, such as but not limited to a digital oversampling receiver adapted to select desired signals and to reject undesired signals. In one embodiment, a wireless communications device is disclosed that comprises an architecture for a receiver front end that obviates the need for high order passive circuitry or RC active circuitry to select desired signals and to reject undesired signals.

Abstract: The invention described herein is directed to different embodiments of a wireless communications device that can be used in many different applications, such as but not limited to a digital oversampling receiver adapted to select desired signals and to reject undesired signals. In one embodiment, a wireless communications device is disclosed that comprises an architecture for a receiver front end that obviates the need for high order passive circuitry or RC active circuitry to select desired signals and to reject undesired signals.

Abstract: The invention described herein is directed to different embodiments of a wireless communications device that can be used in many different applications, such as but not limited to a digital oversampling receiver adapted to select desired signals and to reject undesired signals. In one embodiment, a wireless communications device is disclosed that comprises an architecture for a receiver front end that obviates the need for high order passive circuitry or RC active circuitry to select desired signals and to reject undesired signals.

Abstract: The invention described herein is directed to different embodiments of a wireless communications device that can be used in many different applications, such as but not limited to a digital oversampling receiver adapted to select desired signals and to reject undesired signals. In one embodiment, a wireless communications device is disclosed that comprises an architecture for a receiver front end that obviates the need for high order passive circuitry or RC active circuitry to select desired signals and to reject undesired signals.

Abstract: A self-tuning filter that is well suited for use as a output digital filter in a direct conversion delta-sigma transmitter is constructed as a high pass finite impulse response filter having a cutoff frequency of twice the desired carrier frequency. The filter is clocked using the same clock as used for the commutatation within the transmitter. The aliasing effect of the digital filter produces a passband centered around the carrier frequency which allows the information contained in the spectrum around the passband to be transmitted, while effectively filtering out the quantization noise produced by the commutation. When the commutator clock frequency is changed in order to change the carrier frequency, the passband automatically moves to track the new carrier frequency. The output filter may be constructed using series connected flip-flops with analog taps and an analog summer connected to respective Q and Q outputs, thereby producing an analog output.

Abstract: A wireless receiver receives a wireless signal by inverting the polarity of an incoming waveform on every one half clock cycle of a conversion clock to produce a commutated waveform and converting said commutated waveform to a series of representative digital values using a delta-sigma modulator clocked by said conversion clock. In this way, the receiver operates over a large dynamic range and the use of automatic gain control in the front end may be eliminated.

Abstract: A wireless receiver receives a wireless signal by inverting the polarity of an incoming waveform on every one half clock cycle of a conversion clock to produce a commutated waveform and converting said commutated waveform to a series of representative digital values using a delta-sigma modulator clocked by said conversion clock. In this way, the receiver operates over a large dynamic range and the use of automatic gain control in the front end may be eliminated.

Abstract: A sample and hold circuit that is coupled to a control voltage source and a signal source has a sampling bridge coupled in series between a first resonant tunneling diode. The bridge comprises a plurality of diodes. The sampling bridge couples an input voltage signal that is to be sampled to a holding capacitor when the sampling bridge is forward biased. The bridge substantially decouples the input voltage signal from the holding capacitor when the sampling bridge diodes are reversed biased. The resonant tunneling diodes when reversed biased allow the bridge to be isolated from the control voltage source to allow the holding capacitor to float at the sampled value of the input voltage.

Abstract: A differential comparator circuit for an Analog-to-Digital Converter (ADC) or other application includes a plurality of differential comparators and a plurality of offset voltage generators. Each comparator includes first and second differentially connected transistor pairs having equal and opposite voltage offsets. First and second offset control transistors are connected in series with the transistor pairs respectively. The offset voltage generators generate offset voltages corresponding to reference voltages which are compared with a differential input voltage by the comparators. Each offset voltage is applied to the offset control transistors of at least one comparator to set the overall voltage offset of the comparator to a value corresponding to the respective reference voltage.

Abstract: A phase locked loop system is described for synchronizaing a clock signal to an incoming digital signal and simultaneously detecting that digital signal. The loop is capable of unaided frequency acquisition, hence eliminating the need for special circuits to "pull" the loop into lock when the incoming data rate differs from the initial frequency of the VCO.

Abstract: An enhancement-mode field effect transistor (ENFET) logic circuit providing greater fan-out capability. The logic circuit employs a conventional common-source inverter section, but additionally incorporates a current-driving section which drives the common-source inverter section. A current-driven inverter logic circuit is realized by employing a second ENFET transistor to drive the gate of the common-source inverter section. A current-driven NOR gate is realized by employing two ENFET transistors in parallel which drive the common-source inverter section. Also a current-driven NAND gate is realized by utilizing a single transistor having two gate inputs to drive the common-source inverter section. The use of sweep-out circuitry allows for control of the operational speed of the device. The logic circuit designs have high fan-out capability compared to the common-source inverter circuit alone.