Abstract: A silicon photon detector device and methodology are provided for detecting incident photons in a partially depleted floating body SOI field-effect transistor (310) which traps charges created by visible and mid infrared light in a floating body region (304) when the silicon photon detector is configured in a detect mode, and then measures or reads the resulting enhanced drain current with a current detector in a read mode.

Abstract: A memory device is disclosed that includes multiple bit cells, whereby each bit cell is capable of being programmed to more than two states. A value stored at the memory device is determined by comparing the information stored at three or more of the bit cells. In an embodiment, the bit cell includes a silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (FET) device, and the information stored at the bit cell can be represented by a corresponding level of charge stored in the body of the device.

Abstract: A silicon photon detector device and methodology are provided for detecting incident photons in a partially depleted floating body SOI field-effect transistor (310) which traps charges created by visible and mid infrared light in a floating body region (304) when the silicon photon detector is configured in a detect mode, and then measures or reads the resulting enhanced drain current with a current detector in a read mode.

Abstract: Various apparatus and methods of testing a semiconductor chip for soft defects are disclosed. In one aspect, a method of testing a semiconductor chip that has a surface and plural circuit structures positioned beneath the surface is provided. An external stimulus is applied to a series of fractional portions of the surface to perturb portions of the plural circuit structures such that at least one of the series of fractional portions is smaller than another of the series of fractional portions. The semiconductor chip is caused to perform a test pattern during the application of external stimulus to each of the fractional portions to determine if a soft defect exists in any of the series of fractional portions.

Abstract: Various methods and apparatus for electrically probe testing a semiconductor chip with circuit perturbation are disclosed. In one aspect, a method of testing is provided that includes contacting a first nano probe to a conductor structure on a first side of a semiconductor chip. The semiconductor chip has plural circuit structures. A external stimulus is applied to a selected portion of the first side of the semiconductor chip to perturb at least one of the plural circuit structures. The semiconductor chip is caused to perform a test pattern during the application of the external stimulus. An electrical characteristic of the semiconductor chip is sensed with the first nano probe during performance of the test pattern.

Abstract: A method includes determining a transmission of a transmissive window and a transmission of a transmissive fluid. In addition, an infrared emission of the transmissive window is determined along with an infrared emission of the transmissive fluid for at least one temperature. In a system that has an infrared sensor and an optical pathway to the infrared sensor, the transmissive window and the transmissive fluid are placed in the optical pathway. A semiconductor chip is placed in the optical pathway proximate the transmissive fluid. Radiation from the optical pathway is measured with the infrared sensor. An emissivity of the semiconductor chip is determined using the measured radiation and the determined transmissions and emissions of the transmissive window and the transmissive fluid.

Abstract: A memory device is disclosed that includes multiple bit cells, whereby each bit cell is capable of being programmed to more than two states. A value stored at the memory device is determined by comparing the information stored at three or more of the bit cells. In an embodiment, the bit cell includes a silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (FET) device, and the information stored at the bit cell can be represented by a corresponding level of charge stored in the body of the device.

Abstract: Various methods and apparatus for electrically probe testing a semiconductor chip with circuit perturbation are disclosed. In one aspect, a method of testing is provided that includes contacting a first nano probe to a conductor structure on a first side of a semiconductor chip. The semiconductor chip has plural circuit structures. A external stimulus is applied to a selected portion of the first side of the semiconductor chip to perturb at least one of the plural circuit structures. The semiconductor chip is caused to perform a test pattern during the application of the external stimulus. An electrical characteristic of the semiconductor chip is sensed with the first nano probe during performance of the test pattern.

Abstract: An infrared sensor system and a method of calibrating the system are disclosed. In one aspect, a method includes determining a transmission of a transmissive window and a transmission of a transmissive fluid. In addition, an infrared emission of the transmissive window is determined along with an infrared emission of the transmissive fluid for at least one temperature. In a system that has an infrared sensor and an optical pathway to the infrared sensor, the transmissive window and the transmissive fluid are placed in the optical pathway. A semiconductor chip is placed in the optical pathway proximate the transmissive fluid. Radiation from the optical pathway is measured with the infrared sensor. An emissivity of the semiconductor chip is determined using the measured radiation and the determined transmissions and emissions of the transmissive window and the transmissive fluid.

Abstract: Various apparatus and methods of testing a semiconductor chip for soft defects are disclosed. In one aspect, a method of testing a semiconductor chip that has a surface and plural circuit structures positioned beneath the surface is provided. An external stimulus is applied to a series of fractional portions of the surface to perturb portions of the plural circuit structures such that at least one of the series of fractional portions is smaller than another of the series of fractional portions. The semiconductor chip is caused to perform a test pattern during the application of external stimulus to each of the fractional portions to determine if a soft defect exists in any of the series of fractional portions.