Abstract: The present invention specifically permits purging and/or sampling of a well but only removing, at most, about 25% of the fluid volume compared to conventional methods and, at a minimum, removing none of the fluid volume from the well.The invention is an isolation assembly with a packer, pump and exhaust, that is inserted into the well. The isolation assembly is designed so that only a volume of fluid between the outside diameter of the isolation assembly and the inside diameter of the well over a fluid column height from the bottom of the well to the top of the active portion (lower annulus) is removed. The packer is positioned above the active portion thereby sealing the well and preventing any mixing or contamination of inlet fluid with fluid above the packer. Ports in the wall of the isolation assembly permit purging and sampling of the lower annulus along the height of the active portion.

Abstract: The present invention specifically permits purging and/or sampling of a well but only removing, at most, about 25% of the fluid volume compared to conventional methods and, at a minimum, removing none of the fluid volume from the well.The invention is an isolation assembly that is inserted into the well. The isolation assembly is designed so that only a volume of fluid between the outside diameter of the isolation assembly and the inside diameter of the well over a fluid column height from the bottom of the well to the top of the active portion (lower annulus) is removed. A seal may be positioned above the active portion thereby sealing the well and preventing any mixing or contamination of inlet fluid with fluid above the packer. Purged well fluid is stored in a riser above the packer. Ports in the wall of the isolation assembly permit purging and sampling of the lower annulus along the height of the active portion.

Abstract: A system and method for dispatching logical central processing units (CPUs) among physical CPUs in a multiprocessor computer system having multiple logical partitions, wherein the cryptographic facilities may not be interchangeable. According to the present invention, the logical CPUs are dispatched among the physical CPUs according to either an affinity, floating, or disabled scheduling method. The affinity scheduling method is used when the crypto facilities are not interchangeable or when non-interchangeable crypto functions are performed. The floating scheduling method is used when the cryptographic facilities are interchangeable and interchangeable crypto functions are performed. The disabled scheduling method is used when the logical CPU is not authorized to issue cryptographic instructions.

Abstract: Asynchronously transfers blocks of data (called pages) between two different electronic media of a data processing system. The different media may be a system main storage and a system expanded storage or a non-volatile external type of storage, either of which use different addressing than the main storage. All of these storages may be made of DRAM or SRAM technology with battery backup when necessary. The invention splits the involvement of a program requesting a page transfer into a pair of instructions per page transfer executing on one or more central processors. The first instruction of a pair starts another processor that controls the asynchronous page transfer, and the second instruction of the pair enables the communication of the end of the page transfer to the program. Neither instruction in the pair interrupts the program for the page transfer. A processor executing the starting instruction is immediately free to execute any other available instructions.

Abstract: A cryptographic facility implements a multiple key part import procedure. The installation manager can verify that a key part has been correctly entered and has not been compromised. The security requirement for the procedure is that no single party can subvert the system security by misusing the procedure. This is accomplished by the use of a control-vector-dependent verification pattern to indicate that each key part has been accepted by using the proper control vector and the use of different key switch positions to specify whether the key part is a master key part or an operational key part and whether the key part is a first part or a subsequent key part. The apparatus provides an automatic reset of the key part register at the completion of each key-entry instruction so that each key part can be imported only once. This prevents the same key part from being imported twice as different key part types. The apparatus also prevents a key part from being combined with itself to create a known key.

Abstract: A working key of a certain key type is to be transmitted from a first system (having a first usage-control value associated with keys of the certain type) and a second system (having a second usage-control value associated with keys of the certain type). A translation control value, associated with the certain key type, is generated, functionally relating the first and second usage-control values. The translation control value is used in a cryptographic function to send or receive the working key between systems, the cryptographic function being designed to produce valid results when the correct translation control value, and usage-control values, are employed, and unpredictable results otherwise. Effectively, the first usage-control value is translated to the second usage-control value.

Abstract: A facility for making dynamic changes to a system master key without stopping the system, and without loss of integrity to ongoing cryptographic operations. A version number is generated and associated with the current master key. A dynamic change is made to the master key, resulting in the then current master key becoming the old master key, and a "new" current master key (with a new version number) being placed into operation. Subsequent cryptographic requests using a supplied key enciphered under the old master key are identified by means of a supplied version number associated with the supplied key. This identification triggers a reencipher operation, reenciphering the supplied key under the now current master key--after which the cryptographic operation proceeds. Unique patterns are generated to verify the contents of the master key registers, and to authorize normal use of the cryptographic facility, and issuers of key-change operations.

Abstract: A method and apparatus is provided to translate the contents of access registers into information for use in performing addressing functions for multiple virtual address spaces. The access registers represent the full addressing capability of the system but do not directly contain the addressing information. The system has a plurality of general purpose registers, a plurality of access registers associated with the general registers, an access list having access list entries which is addressed by the contents of the access register, memory storage for holding address space number second table entries (ASTE), where the contents of the access list entry locate the ASTE and where the ASTE contains the addressing information needed to translate a virtual address when combined with the contents of a general purpose register. Access register translation (ART) consists of the process of determining addressing information by using the access list entry and the ASTE.

Abstract: Cryptographic PIN processing is achieved in an improved manner by associating control vectors with the PIN generating (verification) keys and PIN encrypting keys which provide authorization for the uses of the keys intended by the originator of the keys. The originator may be the local cryptographic facility (CF) and a utility program under the control of a security administrator, or the originator may be another network node which uses the key management methods described in the above-referenced copending patent applications to distribute said keys.Among the uses specified by the control vector are limitations on the authority to use the associated key with certain PIN processing instructions, such as PIN generation, verification, translation and PIN block creation. Furthermore, the control vector may limit the authority of certain instructions to process clear PIN inputs (such as in PIN verification).

Abstract: A vector processor is disclosed which processes vectors that can have more elements than a vector register can contain at one time. Vectors are processed in sections in which the section size is determined by the number of element locations in a vector register. A vector count register controls the number of elements processed by each vector instruction. A vector interruption index points to the first or next element in a vector to be processed by a vector instruction either when it is first issued or when it is re-issued following an interruption of the vector instruction. A general purpose (length) register contains the entire length of the vector to be processed. A single instruction, which starts a vector sectioning loop, provides for the smaller of the section size or the content of the length register to be loaded into the vector count register.

Abstract: The invention relates to vector registers (VRs) which have associated therewith a vector status register (VSR) that includes VR status information in the form of vector in-use and change bits for saving and restoring (the contents of) the VRs. When the vector in-use bit for a VR is zero, the saving and subsequent restoring of the VR is eliminated because the VR is known to contain all zeros. This reduces program switching time. The vector change bit for a VR serves to reduce switching time still further by permitting the saving of a VR to be eliminated when its vector in-use bit is one but the vector change bit is zero. Although such a VR is in use, its content has not been changed since the last restore from the same save area in storage. The previously saved information is still valid. The vector change bits do not affect the restoring of vector registers and, therefore, do not reduce the restore time.

Abstract: An electrical connector for electrically interconnecting conductive pads on a printed circuit board and an electronic package located in an opening in the board and for biasing the electronic package against a cooling substructure on which it rests. More particularly, the connector includes a housing having downwardly extending walls for abutting and biasing the electronic package against the substructure and a plurality of contact elements having spring members which electrically engage respective conductive pads on the electronic package and surrounding circuit board.

Abstract: The disclosure describes a separate trace table for each CPU in an MP to avoid inter-CPU interference in making trace table entries for explicit and implicit tracing instructions enabled by flag bits in a control register (CR). Explicit tracing entries are made for an enabled explicit tracing instruction. Implicit tracing entries are made for predetermined instructions (when enabled for tracing) which do not have tracing as their primary purpose. A storage operand of the trace instruction contains a disablement field and optionally may contain an enablement-controlling class field to improve the integrity of traceable programs. A time stamp and range of general register contents is provided in each trace table entry for a tracing instruction. The time stamp enables all trace tables in an MP system to be later merged into a single trace table whenever required.

Abstract: The embodiments relate to special controls in a processor which eliminate synonym entries in a translation lookaside buffer (DLAT) for a system which has DLAT entries that can concurrently translate virtual addresses in multiple address spaces into real main storage addresses. The controls provide a common space bit in any segment table entry (STE) or alternatively in any page table entry (PTE) in any private address space to indicate whether the segment or page, respectively, contains programs and data private to the address space or shared by all address spaces. Each DLAT entry contains a common/private storage indictor which is set to the state of the common space bit in the STE or PTE used in an address translation loaded into the DLAT entry. When the entry is read, the private/common storage indicator controls whether the DLAT can only be used by the address space identified in the DLAT, or by all address spaces.