Abstract: An apparatus, system, and method are disclosed for proxy coupling management. A proxy template module transparently offloads a task from a native data processing system to an equivalent task on a remote data processing system. A proxy generation module fills in the proxy template with information, such as specification of an offload task that is a remote equivalent of the native task, to generate a proxy of the native task. An offload agent module receives a request from the proxy to perform the offload task on the remote data processing system.

Abstract: An apparatus, system, and method are disclosed for proxy coupling management. A proxy template module transparently offloads a task from a native data processing system to an equivalent task on a remote data processing system. A proxy generation module fills in the proxy template with information, such as specification of an offload task that is a remote equivalent of the native task, to generate a proxy of the native task. An offload agent module receives a request from the proxy to perform the offload task on the remote data processing system.

Abstract: An apparatus, system, and method are disclosed for offloading data processing. An offload task hosted on a first data processing system provides internal functionality substantially equivalent to that of a second task 304 hosted on a second data processing system of a potentially different architecture. A proxy task hosted on the second data processing system provides an external interface substantially equivalent to that of the second task. A communication mechanism between the first and second data processing systems may be comprised of a network, shared storage, and shared memory. The proxy task substantially replaces the second task, delegating the internal functionality of the second task to the offload task via mapping of arguments and accessing and translating of input and output data as required.

Abstract: A computer system including a plurality of physical processors (CPs) having physical processor performances (PCPs), a plurality of logical processors (LCPs), a plurality of logical partitions (LPARs) where each partition includes one or more of the logical processors (LCPs), and a system assist processor having a control element. The control element controls the virtualization of the physical processors (CPs), the logical partitions (LPARs) and the logical processors (LCPs) and allocates the physical processor performances (PCPs) to the logical partitions (LPARs). The control element operates to exclusively bind logical processors (LCPs) to the physical processors (CPs). For a logical processor (LCP) exclusively bound to a physical processor (CP), the logical processor (LCP) has exclusive use of the underlying physical processor (CP) and no other logical processor (LCP) can be dispatched on the underlying physical processor (CP) even if the underlying physical processor (CP) is otherwise available.

Abstract: An apparatus, system, and method are disclosed for self-cleaning dust removal. The apparatus may be provided with a brush housing 202 having an opening 204, one or more axles 206 disposed around the opening 204, and a plurality of brush fibers 208 emanating from the one or more axles 206 that rotate inward into the opening 204. In addition, the system may include a scraping edge 106, disposed around the opening 204, farther into the brush housing 202 than the one or more axles 206, that scrapes 1408 dust off of the brush fibers 208 as they rotate inward against the scraping edge 106, and a vacuum cleaner intake port 110 inside the brush housing 202 that draws 1410 dust from off and about the brush fibers 208 as they rotate inward 1406. The system may further include a handle 112 connected to the brush housing 202 and a switch 114.

Abstract: An apparatus, system, and method are disclosed for self-cleaning dust removal. The apparatus may be provided with a brush housing 202 having an opening 204, one or more axles 206 disposed around the opening 204, and a plurality of brush fibers 208 emanating from the one or more axles 206 that rotate inward into the opening 204. In addition, the system may include a scraping edge 106, disposed around the opening 204, farther into the brush housing 202 than the one or more axles 206, that scrapes 1408 dust off of the brush fibers 208 as they rotate inward against the scraping edge 106, and a vacuum cleaner intake port 110 inside the brush housing 202 that draws 1410 dust from off and about the brush fibers 208 as they rotate inward 1406. The system may further include a handle 112 connected to the brush housing 202 and a switch 114.

Abstract: An apparatus, system, and method are disclosed for offloading data processing. An offload task hosted on a first data processing system provides internal functionality substantially equivalent to that of a second task 304 hosted on a second data processing system of a potentially different architecture. A proxy task hosted on the second data processing system provides an external interface substantially equivalent to that of the second task. A communication mechanism between the first and second data processing systems may be comprised of a network, shared storage, and shared memory. The proxy task substantially replaces the second task, delegating the internal functionality of the second task to the offload task via mapping of arguments and accessing and translating of input and output data as required.

Abstract: An apparatus, system, and method are disclosed for offloading data processing. An offload task 306 hosted on a first data processing system 300-1 provides internal functionality substantially equivalent to that of a second task 304 hosted on a second data processing system 300-2 of a potentially different architecture. A proxy task 308 hosted on the second data processing system 300-2 provides an external interface substantially equivalent to that of the second task 304. A communication mechanism 322 between the first and second data processing systems 300 may be comprised of a network 424, shared storage 422, and shared memory 426. The proxy task 308 substantially replaces the second task 304, delegating the internal functionality of the second task 304 to the offload task 306 via mapping 506 of arguments and accessing 514 and 714 and translating 518 and 710 of input 510 and output 706 data as required.

Abstract: A computer system including a plurality of physical processors (CPs) having physical processor performances (PCPs), a plurality of logical processors (LCPs), a plurality of logical partitions (LPARs) where each partition includes one or more of the logical processors (LCPs), and a system assist processor having a control element. The control element controls the virtualization of the physical processors (CPs), the logical partitions (LPARs) and the logical processors (LCPs) and allocates the physical processor performances (PCPs) to the logical partitions (LPARs). The control element operates to exclusively bind logical processors (LCPs) to the physical processors (CPs). For a logical processor (LCP) exclusively bound to a physical processor (CP), the logical processor (LCP) has exclusive use of the underlying physical processor (CP) and no other logical processor (LCP) can be dispatched on the underlying physical processor (CP) even if the underlying physical processor (CP) is otherwise available.

Abstract: A computer system including a plurality of physical processors (CPs) having physical processor performances (PCPs), a plurality of logical processors (LCPs), a plurality of logical partitions (LPARs) where each partition includes one or more of the logical processors (LCPs), and a system assist processor having a control element. The control element controls the virtualization of the physical processors (CPs), the logical partitions (LPARs) and the logical processors (LCPs) and allocates the physical processor performances (PCPs) to the logical partitions (LPARs). The control element operates to exclusively bind logical processors (LCPs) to the physical processors (CPs). For a logical processor (LCP) exclusively bound to a physical processor (CP), the logical processor (LCP) has exclusive use of the underlying physical processor (CP) and no other logical processor (LCP) can be dispatched on the underlying physical processor (CP) even if the underlying physical processor (CP) is otherwise available.

Abstract: A method and system for a decentralized distributed storage data system. A plurality of central processors each having a cache may be directly coupled to a shared set of data storage units. A high speed network may be used to communicate at a physical level between the central processors. A coherency protocol may be used to communicate at a logical level between the central processors.

Abstract: An apparatus, system, and method are disclosed for self-cleaning dust removal. The apparatus may be provided with a brush housing 202 having an opening 204, one or more axles 206 disposed around the opening 204, and a plurality of brush fibers 208 emanating from the one or more axles 206 that rotate inward into the opening 204. In addition, the system may include a scraping edge 106, disposed around the opening 204, farther into the brush housing 202 than the one or more axles 206, that scrapes 1408 dust off of the brush fibers 208 as they rotate inward against the scraping edge 106, and a vacuum cleaner intake port 110 inside the brush housing 202 that draws 1410 dust from off and about the brush fibers 208 as they rotate inward 1406. The system may further include a handle 112 connected to the brush housing 202 and a switch 114.

Abstract: A method and system of storing to an instruction stream with a multiprocessor or multiple-address-space system is disclosed. A central processing unit may cache instructions in a cache from a page of primary code stored in a memory storage unit. The central processing unit may execute cached instructions from the cache until a serialization operation is executed. The central processing unit may check in a message queue for a notification message indicating potential storing to the page. If the notification message is present in the message queue, cached instructions from the page are invalidated.

Abstract: A method of translating a virtual address to a real address. A first entry from a first table or other source includes a plurality of second table addressing parameters including a second table origin and a second table length. A second table address is provided by combining the second table origin with a second table index from the virtual address. The second table address is used for indexing into the second table to access a second table entry in the second table. A post-comparing of one or more of the second table addressing parameters with the second table index from the virtual address is performed to form one or more results. The virtual address processing continues using the second table entry if the comparing provides an affirmative result and if the comparing provides a negative result an exception is taken.

Abstract: A method and system of sparse table compaction is disclosed. A repeating data pattern may be detected in a large data structure, identifying the large data structure as a sparse table. The large data structure is stored in a virtual memory as a series of virtual data pages. Multiple repeating virtual data pages may be mapped to a single physical data page on a multiple-to-one basis. Unique virtual data page may be mapped to a unique physical data page on a one-to-one basis.

Abstract: An apparatus, system, and method are disclosed for offloading data processing. An offload task 306 hosted on a first data processing system 300-1 provides internal functionality substantially equivalent to that of a second task 304 hosted on a second data processing system 300-2 of a potentially different architecture. A proxy task 308 hosted on the second data processing system 300-2 provides an external interface substantially equivalent to that of the second task 304. A communication mechanism 322 between the first and second data processing systems 300 may be comprised of a network 424, shared storage 422, and shared memory 426. The proxy task 308 substantially replaces the second task 304, delegating the internal functionality of the second task 304 to the offload task 306 via mapping 506 of arguments and accessing 514 and 714 and translating 518 and 710 of input 510 and output 706 data as required.

Abstract: A computer system including a plurality of physical processors (CPs) having physical processor performances (PCPs), a plurality of logical processors (LCPs), a plurality of logical partitions (LPARs) where each partition includes one or more of the logical processors (LCPs), and a system assist processor having a control element. The control element controls the virtualization of the physical processors (CPs), the logical partitions (LPARs) and the logical processors (LCPs) and allocates the physical processor performances (PCPs) to the logical partitions (LPARs). The control element operates to exclusively bind logical processors (LCPs) to the physical processors (CPs). For a logical processor (LCP) exclusively bound to a physical processor (CP), the logical processor (LCP) has exclusive use of the underlying physical processor (CP) and no other logical processor (LCP) can be dispatched on the underlying physical processor (CP) even if the underlying physical processor (CP) is otherwise available.

Abstract: A method and system of storing to an instruction stream with a multiprocessor or multiple-address-space system is disclosed. A central processing unit may cache instructions in a cache from a page of primary code stored in a memory storage unit. The central processing unit may execute cached instructions from the cache until a serialization operation is executed. The central processing unit may check in a message queue for a notification message indicating potential storing to the page. If the notification message is present in the message queue, cached instructions from the page are invalidated.

Abstract: A method and system of organizing a cache memory system based on a temporal-access pattern is disclosed. One or more data entries may be stored in a memory. One or more cache entries of the one or more data entries may be stored in a temporal cache. The one or more cache entries may be physically organized based on a temporal access pattern. A cache entry of the one or more cache entries may be based upon a condition.

Abstract: A method of translating a virtual address to a real address. A first entry from a first table or other source includes a plurality of second table addressing parameters including a second table origin and a second table length. A second table address is provided by combining the second table origin with a second table index from the virtual address. The second table address is used for indexing into the second table to access a second table entry in the second table. A post-comparing of one or more of the second table addressing parameters with the second table index from the virtual address is performed to form one or more results. The virtual address processing continues using the second table entry if the comparing provides an affirmative result and if the comparing provides a negative result an exception is taken.