Abstract: There is disclosed in one example a processor, including: a protected runtime mode (PRM) module to receive a PRM interrupt and to: suspend operation of a software task executing on the processor; save processor state information; place the microprocessor into PRM; access a PRM handler in a designated PRM memory region, wherein the PRM handler comprises a platform specific task; restore the processor state; and resume operation of the software task.

Abstract: A systems and methods for dynamic address based minoring are disclosed. A system may include a processor, comprising a mirror address range register to store data indicating a location and a size of a first portion of a system memory to be mirrored. The processor may further include a memory controller coupled to the mirror address range register and including circuitry to cause a second portion of the system memory to mirror the first portion of the system memory.

Abstract: There is disclosed in one example a processor, including: a protected runtime mode (PRM) module to receive a PRM interrupt and to: suspend operation of a software task executing on the processor; save processor state information; place the microprocessor into PRM; access a PRM handler in a designated PRM memory region, wherein the PRM handler comprises a platform specific task; restore the processor state; and resume operation of the software task.

Abstract: An apparatus and method are described for system physical address to memory module address translation. For example, one embodiment of an apparatus comprises: a fetch circuit of a core to fetch a system physical address (SPA) translate instruction from memory; a decode circuit of the core to decode the SPA translate instruction; a first register to store an SPA associated with the SPA translate instruction; a memory controller comprising one or more channel controllers to initiate a translation using the SPA, the memory controller to transmit a translation request to a first channel controller; the first channel controller to synthesize a response including dual in-line memory module (DIMM) address information; and a second register to store the DIMM address information to be used to identify the DIMM during subsequent memory transactions.

Abstract: An apparatus and method are described for system physical address to memory module address translation. For example, one embodiment of an apparatus comprises: a fetch circuit of a core to fetch a system physical address (SPA) translate instruction from memory; a decode circuit of the core to decode the SPA translate instruction; a first register to store an SPA associated with the SPA translate instruction; a memory controller comprising one or more channel controllers to initiate a translation using the SPA, the memory controller to transmit a translation request to a first channel controller; the first channel controller to synthesize a response including dual in-line memory module (DIMM) address information; and a second register to store the DIMM address information to be used to identify the DIMM during subsequent memory transactions.

Abstract: A systems and methods for dynamic address based minoring are disclosed. A system may include a processor, comprising a mirror address range register to store data indicating a location and a size of a first portion of a system memory to be mirrored. The processor may further include a memory controller coupled to the mirror address range register and including circuitry to cause a second portion of the system memory to mirror the first portion of the system memory.

Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for a Unified Extensible Firmware Interface (UEFI) with durable storage to provide memory write persistence, for example, in the event of power loss. The system may include a processor to host the firmware interface which may be configured to control access to system variables in a protected region of a volatile memory. The system may also include a power management circuit to provide power to the processor and further to provide a power loss indicator to the firmware interface. The system may also include a reserve energy storage module to provide power to the processor in response to the power loss indicator. The firmware interface is further configured to copy the system variables from the volatile memory to a non-volatile memory in response to the power loss indicator.

Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for a Unified Extensible Firmware Interface (UEFI) with durable storage to provide memory write persistence, for example, in the event of power loss. The system may include a processor to host the firmware interface which may be configured to control access to system variables in a protected region of a volatile memory. The system may also include a power management circuit to provide power to the processor and further to provide a power loss indicator to the firmware interface. The system may also include a reserve energy storage module to provide power to the processor in response to the power loss indicator. The firmware interface is further configured to copy the system variables from the volatile memory to a non-volatile memory in response to the power loss indicator.