Patents by Inventor Ronald P. Bourque

Ronald P. Bourque has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7804136
    Abstract: A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is characterized as high-frequency power (supplied by an RF generator at 13.56 MHz). The FET device may also include NFET gate structures. A blocking layer is deposited over the NFET gate structures so that the nitride layer overlies the blocking layer; after the blocking layer is removed, the nitride layer is not in contact with the NFET gate structures. The nitride layer has a thickness in the range of about 300-2000 ?.
    Type: Grant
    Filed: October 19, 2007
    Date of Patent: September 28, 2010
    Assignee: International Business Machines Corporation
    Inventors: Richard A. Conti, Ronald P. Bourque, Nancy R. Klymko, Anita Madan, Michael C. Smits, Roy H. Tilghman, Kwong Hon Wong, Daewon Yang
  • Patent number: 7491660
    Abstract: A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is characterized as high-frequency power (supplied by an RF generator at 13.56 MHz). The FET device may also include NFET gate structures. A blocking layer is deposited over the NFET gate structures so that the nitride layer overlies the blocking layer; after the blocking layer is removed, the nitride layer is not in contact with the NFET gate structures. The nitride layer has a thickness in the range of about 300-2000 ?.
    Type: Grant
    Filed: October 17, 2007
    Date of Patent: February 17, 2009
    Assignees: International Business Machines Corporation, Novellus Systems. Inc.
    Inventors: Richard A. Conti, Ronald P. Bourque, Nancy R. Klymko, Anita Madan, Michael C. Smits, Roy H. Tilghman, Kwong Hon Wong, Daewon Yang
  • Patent number: 7462527
    Abstract: A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is characterized as high-frequency power (supplied by an RF generator at 13.56 MHz). The FET device may also include NFET gate structures. A blocking layer is deposited over the NFET gate structures so that the nitride layer overlies the blocking layer; after the blocking layer is removed, the nitride layer is not in contact with the NFET gate structures. The nitride layer has a thickness in the range of about 300-2000 ?.
    Type: Grant
    Filed: July 6, 2005
    Date of Patent: December 9, 2008
    Assignees: International Business Machines Corporation, Novellus Systems, Inc.
    Inventors: Richard A. Conti, Ronald P. Bourque, Nancy R. Klymko, Anita Madan, Michael C. Smits, Roy H. Tilghman, Kwong Hon Wong, Daewon Yang