Abstract: Methods for accessing full bandwidth in an asynchronous data transfer and source traffic control system include permitting some bus users (e.g. networks cards) to access both odd and even frames while permitting other bus users (e.g. subscriber line cards) to access only odd or even frames. An apparatus according to the invention supports line cards numbering up to 32?(2×the number of network cards). An exemplary embodiment shows a single network card coupled to an OC-12 network link and twenty asymmetric digital subscriber line cards.

Abstract: Methods for implementing a backpressure mechanism in an asynchronous data transfer and source traffic control system include detecting when a bus user is experiencing congestion and preventing other bus users from sending cells over the bus. According to a first embodiment, if congestion is detected for two consecutive frames, the arbiter is inhibited from granting access to any bus user for one frame. According to a second embodiment, if congestion is detected during any frame, all the bus users are prevented from transmitting low priority traffic until congestion is absent for four consecutive frames. An apparatus for performing the methods is also disclosed.

Abstract: Methods and apparatus for providing redundancy in an asynchronous data transfer and source traffic control system include configuring a primary client and a backup client with the same receive address but different transmit addresses. This allows both clients to receive the same traffic flows by utilizing a common receive address while maintaining independent transmit identity allowing each client to communicate with other clients in the system. The methods of the present invention are compatible with a CellBus® system operating in either 16-client mode or 32-client mode.

Abstract: Methods and apparatus for supporting multiple UTOPIA bus masters on a single UTOPIA bus include coupling two UTOPIA bus masters via three signal lines (Ready, Request, and Grant), designating one of the masters a primary master and the other a secondary master, and coupling both bus masters to the same UTOPIA bus. When receiving cells from the UTOPIA bus, both masters accept cells and screen them (with a lookup table) to determine which cells are addressed to them. When transmitting cells, the primary master normally controls polling and PHY selection. The secondary master asserts the Request line during polling to indicate that it has a cell to send to a PHY that has responded positively to the polling. In response to the Request signal, the primary master asserts the Grant line and control of the bus is given to the secondary master for the next cell cycle. The presently preferred embodiment utilizes an arbitration scheme to assure fairness in allocating control of the bus.

Abstract: Methods for allocating bandwidth among MCR and best effort connections include listing MCR connections in an MCR service list and best efforts connection in a best efforts (BE) service list. Assigning an MCR value to each MCR connection and setting a Cell Count Register (CCR) with it. During a service interval, dequeueing each MCR connection queue in round robin fashion according to the MCR service list and decrementing the associated CCR. If the CCR reaches zero before the end of the service interval and there are still cells in the queue, the connection is moved from the MCR service list to the BE service list for the remainder of the service interval. If the CCR reaches zero before the end of the service interval and/or there are no cells remaining in the queue, the connection is removed from the MCR service list.

Abstract: Methods and apparatus for extending the transmission range of a UTOPIA ATM (or packet) interface include providing two UTOPIA extension devices, one for coupling a PHY layer device to a transmission cloud and one for coupling an ATM layer (or LINK layer) device to the transmission cloud. Each device includes a UTOPIA interface emulator, a link controller, and a media transceiver. The media transceiver can be made to support various media such as a backplane, copper cable, optical fiber, or a wireless medium. The UTOPIA extension device preferably includes a UTOPIA inlet buffer, a UTOPIA outlet buffer, an inlet clock decoupling buffer, an outlet clock decoupling buffer, and a flow control module. The UTOPIA inlet and outlet buffers are used for traffic management and the clock decoupling buffers allow the UTOPIA interface emulator and the link controller to operate in different clock domains. The link controller provides error control and backpressure delivery to support flow control.

Abstract: An apparatus for guaranteeing MCR in an ATM device includes at least one queue for each service category, a scheduler for dequeuing cells from the queues, a queue status block for indicating which queues are empty, and an MCR service block. The MCR service block includes a plurality of timers, at least one for each service category. According to the methods of the invention, an MCR value is selected for each queue (or service category) and a timer in the MCR service block is set according to the MCR value. The scheduler dequeues cells in strict priority from non-empty queues as determined by the queue status block. The scheduler is preempted, however, by the MCR service block when a queue fails to be serviced before its associated timer expires. The arrangement of queues and associated timers is subject to alternate embodiments.

Abstract: Methods and apparatus for extending the transmission range of a UTOPIA ATM (or packet) interface include providing two UTOPIA extension devices, one for coupling a PHY layer device to a transmission cloud and one for coupling an ATM layer (or LINK layer) device to the transmission cloud. Each device includes a UTOPIA interface emulator, a link controller, and a media transceiver. The media transceiver can be made to support various media such as a backplane, copper cable, optical fiber, or a wireless medium. The UTOPIA extension device preferably includes a UTOPIA inlet buffer, a UTOPIA outlet buffer, an inlet clock decoupling buffer, an outlet clock decoupling buffer, and a flow control module. The UTOPIA inlet and outlet buffers are used for traffic management and the clock decoupling buffers allow the UTOPIA interface emulator and the link controller to operate in different clock domains. The link controller provides error control and backpressure delivery to support flow control.

Abstract: Methods for implementing a backpressure mechanism in an asynchronous data transfer and source traffic control system include detecting when a bus user is experiencing congestion and preventing other bus users from sending cells over the bus. According to a first embodiment, if congestion is detected for two consecutive frames, the arbiter is inhibited from granting access to any bus user for one frame. According to a second embodiment, if congestion is detected during any frame, all the bus users are prevented from transmitting low priority traffic until congestion is absent for four consecutive frames.

Abstract: Methods and apparatus for providing redundancy in an asynchronous data transfer and source traffic control system include configuring a primary client and a backup client with the same receive address but different transmit addresses. This allows both clients to receive the same traffic flows by utilizing a common receive address while maintaining independent transmit identity allowing each client to communicate with other clients in the system. The methods of the present invention are compatible with a CellBus® system operating in either 16-client mode or 32-client mode.

Abstract: A multiport non-blocking high capacity ATM and packet switch is a single chip switching solution for ATM and packet systems. It is capable of 8×8 switching of 800 Mbit/s per port in both directions. The ports support UTOPIA Level 2 interfaces. The switch is non-blocking and lossless, incorporating a backpressure mechanism for eliminating congestion toward any one port. The switch supports prioritized and variable size cell and packet switching.

Abstract: Methods for enhancing the efficiency of SDRAM include dividing all of the data blocks into at least two parts and storing each part in a different bank of memory. Specifically, the first part of each data block is stored in the first bank of memory and subsequent parts are stored in other banks. Since every data block begins in one bank and ends in another bank, no memory bank is ever accessed twice consecutively. In this manner it is always possible to perform precharge and row activation for the next data access while finishing the present data access. The methods of the invention are illustrated in conjunction with the storage and retrieval of ATM cells.

Abstract: An apparatus for guaranteeing MCR in an ATM device includes at least one queue for each service category, a scheduler for dequeuing cells from the queues, a queue status block for indicating which queues are empty, and an MCR service block. The MCR service block includes a plurality of timers, at least one for each service category. According to the methods of the invention, an MCR value is selected for each queue (or service category) and a timer in the MCR service block is set according to the MCR value. The scheduler dequeues cells in strict priority from non-empty queues as determined by the queue status block. The scheduler is preempted, however, by the MCR service block when a queue fails to be serviced before its associated timer expires. The arrangement of queues and associated timers is subject to alternate embodiments.

Abstract: A multiport non-blocking high capacity ATM and packet switch is a single chip switching solution for ATM and packet systems. It is capable of 8×8 switching of 800 Mbit/s per port in both directions. The ports support UTOPIA Level 2 interfaces. The switch is non-blocking and lossless, incorporating a backpressure mechanism for eliminating congestion toward any one port. The switch supports prioritized and variable size cell and packet switching.

Abstract: Methods and apparatus for supporting multiple UTOPIA bus masters on a single UTOPIA bus include coupling two UTOPIA bus masters via three signal lines (Ready, Request, and Grant), designating one of the masters a primary master and the other a secondary master, and coupling both bus masters to the same UTOPIA bus. When receiving cells from the UTOPIA bus, both masters accept cells and screen them (with a lookup table) to determine which cells are addressed to them. When transmitting cells, the primary master normally controls polling and PHY selection. The secondary master asserts the Request line during polling to indicate that it has a cell to send to a PHY that has responded positively to the polling. In response to the Request signal, the primary master asserts the Grant line and control of the bus is given to the secondary master for the next cell cycle. The presently preferred embodiment utilizes an arbitration scheme to assure fairness in allocating control of the bus.

Abstract: Methods for allocating bandwidth among MCR and best effort connections include listing MCR connections in an MCR service list and best efforts connection in a best efforts (BE) service list. Assigning an MCR value to each MCR connection and setting a Cell Count Register (CCR) with it. During a service interval, dequeueing each MCR connection queue in round robin fashion according to the MCR service list and decrementing the associated CCR. If the CCR reaches zero before the end of the service interval and there are still cells in the queue, the connection is moved from the MCR service list to the BE service list for the remainder of the service interval. If the CCR reaches zero before the end of the service interval and/or there are no cells remaining in the queue, the connection is removed from the MCR service list.

Abstract: The invention utilizes two-stage shaping and two-priority queuing thereby allowing both shaped and unshaped virtual circuits to be provisioned in a single virtual path. For each VP, a separate dynamic buffer is set up for each shaped VC and unshaped VC within the VP. The shaped cells stored in dynamic buffers are dequeued via VC scheduling (first stage shaper) to a high priority queue according to the shaped VC contracts, and the unshaped cells stored in dynamic buffers are dequeued in a round robin manner to a low priority queue. The outputs of both the high priority queue and the low priority queue are passed to a second stage shaper where cells from the high priority queue are scheduled according to the VP contract, and cells from the low priority queue are also scheduled according to the VP contract, but only when VP bandwidth is not being used by the high priority cells.