Abstract: The scan flipflops on a semiconductor chip are stitched together to form one or more scan chains, located in one or more standard cell placement regions, after the optimal physical location of each scan flip-flop has been determined. As a result, the total length of the scan chain wires is substantially reduced, thereby reducing on-chip wiring congestion, flip-flop load capacitance, and flipflop power dissipation.

Abstract: An electrostatic discharge protection circuit (ESD protection circuit) provides ESD protection to all NMOS/PMOS transistors that are connected to the pins of a CMOS integrated circuit (IC). The ESD protection circuit will protect the CMOS IC against an ESD event, regardless of whether the CMOS IC is powered up, or powered down.

Abstract: A high voltage CMOS output buffer is constructed from low voltage CMOS transistors. The output buffer employs a series of unique CMOS inverter stages, each of which contains a switched PMOS transistor, one or more voltage drop blocks, and a switched NMOS transistor. The voltage drop blocks are composed of stacked PMOS transistors that are diode-connected—i.e., the PMOS gate terminal is connected to the PMOS drain terminal, and the PMOS body (N-well) terminal is connected to the PMOS source terminal. The diode-connected PMOS transistors reduce the voltage across the transistor gate oxide to a safe value, for all internal PMOS/NMOS transistors inside the CMOS output buffer.

Abstract: A semiconductor chip is ESD protected, in part, by utilizing floating lateral clamp diodes. Unlike conventional clamp diodes, which are based upon parasitic bipolar devices associated with large MOS transistors, the floating lateral clamp diodes utilize a well formed in the substrate as the cathode, and a plurality of regions of the opposite conductivity type which are formed in the well as the anode.

Abstract: A CMOS based input buffer suitable for use with PECL or LVPECL voltage levels is described. The input buffer utilizes a differential voltage comparator that employs positive feedback to provide input hysteresis, symmetric headroom and increased noise immunity. In addition, the input buffer can utilize a reference voltage that is substantially constant over process, voltage, and temperature.

Abstract: A high voltage CMOS output buffer is constructed from low voltage CMOS transistors. The output buffer employs a series of unique CMOS inverter stages, each of which contains a switched PMOS transistor, one or more voltage drop blocks, and a switched NMOS transistor. The voltage drop blocks are composed of stacked PMOS transistors that are diode-connected—i.e., the PMOS gate terminal is connected to the PMOS drain terminal, and the PMOS body (N-well) terminal is connected to the PMOS source terminal. The diode-connected PMOS transistors reduce the voltage across the transistor gate oxide to a safe value, for all internal PMOS/NMOS transistors inside the CMOS output buffer.

Abstract: A CMOS based input buffer suitable for use with PECL or LVPECL voltage levels is described. The input buffer utilizes a differential voltage comparator that employs positive feedback to provide input hysteresis, symmetric headroom and increased noise immunity. In addition, the input buffer can utilize a reference voltage that is substantially constant over process, voltage, and temperature.

Abstract: A 3-dimensional flipflop timing model is described, which allows a flipflop to be presented with a smaller setup time in comparison to a 2-dimensional timing model. Because of this, fewer timing errors will be encountered during chip timing analysis, fewer timing errors will have to be fixed, and the user can often avoid redesigning logic that fails to meet its timing specs, thus saving valuable design time. Furthermore, in many cases, the user can avoid the necessity of using larger standard cells that employ larger transistor sizes, thus minimizing chip size and chip power dissipation.

Abstract: The scan flipflops on a semiconductor chip are stitched together to form one or more scan chains, located in one or more standard cell placement regions, after the optimal physical location of each scan flip-flop has been determined. As a result, the total length of the scan chain wires is substantially reduced, thereby reducing on-chip wiring congestion, flip-flop load capacitance, and flipflop power dissipation.

Abstract: A power-on reset circuit includes a trigger circuit that indicates when a power supply has been turned on, and when the supply has reached a voltage level that is sufficient for normal chip operation. For chips that contain a crystal oscillator, the power-on reset circuit also includes logic that determines the duration of the crystal warm-up delay.

Abstract: A zero crossing detector employs carry save adders combined with fully pipelined logic to provide two-bit, three-bit or four-bit zero crossing detection. The detector offers the advantages of very high operating speed, very low power dissipation, low adder cell count and reduced chip area.

Abstract: A chip is initialized by a power-on reset circuit, after a turned-on power supply has reached a voltage level sufficient for normal chip operation. Logic gating is used to provide a glitch-free trigger signal that prevents erroneous chip re-initialization due to VDD glitches, and to provide a crystal warm-up delay that can be quickly tested without the use of dedicated I/O pins.

Abstract: A edge triggered flipflop tolerates arbitrarily slow clock edge rates by utilizing complex gates, with weighted transistors, to electrically isolate the master latch from the data inputs, before the master latch and the slave latch are electrically connected together, and to electrically isolate the master latch from the slave latch, before the master latch and the data inputs are electrically connected together.

Abstract: Pseudo area values, which represent standard cell power dissipation, are substituted for physical standard cell areas in a standard cell library. As a result, when a logic synthesizer synthesizes a gate level netlist from hardware description language (HDL) code, the synthesized netlist will describe a logic block that has minimal power dissipation.

Abstract: A low power, high speed full adder cell is described. This cell supports all possible combinations of active high/active low input/output signal polarity (32 different combinations), without adding extra inverters or extra transistors. The cell makes liberal use of complementary metal oxide semiconductor (CMOS) transmission gates in order to minimize the number of transistors used, and to minimize their stacking. This significantly decreases the total transistor gate area consumed, resulting in minimal power dissipation and minimal cell size.

Abstract: The power dissipation, logic complexity and chip area of a thermometer controller are all significantly reduced by utilizing a series of scan flip-flops that are connected together to form a bi-directional shift register, along with a gated clock signal that clocks the series of scan flip-flops.

Abstract: The rising edge triggered flip-flops and falling edge triggered flip-flops in one or more clock domains of a target system can be simultaneously initialized to predetermined logic states by activating the flip-flop set/clear inputs, freezing the flip-flop clock signals high or low, subsequently deactivating the flip-flop set/clear inputs, and then re-enabling the clock signals.

Abstract: A gated clock circuit outputs a gated clock signal in response to a master clock signal and a control signal that has a rising or falling edge that follows a rising edge of the master clock signal by a delay. The gated clock signal has a pulse width that is equal to, and in phase with, the pulse width of a master clock signal, while at the same time substantially increasing the maximum value of the delay.

Abstract: An electrostatic discharge (ESD) protection circuit includes a diode that is connected between a pad and a power supply line, and a negative protection circuit that is connected between the pad and a ground line. The negative protection circuit allows the pad voltage to go below ground during normal (non-ESD) operation, and provides adequate ESD protection during an ESD event.

Abstract: A low power tap multiplier multiplies a m-bit multiplier and a n-bit multiplicand to output a p-bit multiplication product. The p-bit product is one bit more than the n-bit multiplicand when the multiplicand is symmetric, and two bits more when the multiplicand is non-symmetric. Since the low power tap multiplier utilizes a minimal number of small unstacked transistors, it consumes less power and requires less silicon area.