Patents by Inventor Ronald Peter Luijten
Ronald Peter Luijten has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210342286Abstract: A coarse-grained reconfigurable array accelerator for solving partial differential equations for problems on a regular grid is provided. The regular grid comprises grid cells which are representative for a physical natural environment wherein a list of physical values is associated with each grid cell. The accelerator comprises configurable processing elements in an accelerator-internal grid connected by an accelerator-internal interconnect system and memory arrays comprising memory cells. The memory arrays are connected to the accelerator-internal interconnect system. Selected ones of the memory arrays are positioned within the accelerator corresponding to positions of the grid cells in the physical natural environment. Thereby, each group of the memory cells is adapted for storing the list of physical values of the corresponding grid cell of the physical natural environment.Type: ApplicationFiled: May 4, 2020Publication date: November 4, 2021Inventors: Ronald Peter Luijten, Gagandeep Singh, Joost VandeVondele
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Patent number: 11163715Abstract: A coarse-grained reconfigurable array accelerator for solving partial differential equations for problems on a regular grid is provided. The regular grid comprises grid cells which are representative for a physical natural environment wherein a list of physical values is associated with each grid cell. The accelerator comprises configurable processing elements in an accelerator-internal grid connected by an accelerator-internal interconnect system and memory arrays comprising memory cells. The memory arrays are connected to the accelerator-internal interconnect system. Selected ones of the memory arrays are positioned within the accelerator corresponding to positions of the grid cells in the physical natural environment. Thereby, each group of the memory cells is adapted for storing the list of physical values of the corresponding grid cell of the physical natural environment.Type: GrantFiled: May 4, 2020Date of Patent: November 2, 2021Assignee: International Business Machines CorporationInventors: Ronald Peter Luijten, Gagandeep Singh, Joost VandeVondele
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Patent number: 10008474Abstract: Embodiments of the invention are directed to an integrated circuit (IC) package assembly, including: one or more printed circuit boards (PCBs); and a set of chip packages, each including: an overmold; and an IC chip, overmolded in the overmold, and wherein: the chip packages are stacked transversely to an average plane of each of the chip packages, thereby forming a stack wherein a main surface of one of the chip packages faces a main surface of another one of the chip packages; and each of the chip packages is laterally soldered to one or more of said one or more PCBs and arranged transversally to each of said one or more PCBs, whereby an average plane of each of said one or more PCBs extends transversely to the average plane of each of the chip packages of the stack. Further embodiments are directed to related devices and fabrication methods.Type: GrantFiled: July 11, 2016Date of Patent: June 26, 2018Assignee: International Business Machines CorporationInventors: Thomas J. Brunschwiler, Andreas Christian Doering, Ronald Peter Luijten, Stefano Sergio Oggioni, Patricia Maria Sagmeister, Martin Leo Schmatz
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Publication number: 20180012864Abstract: Embodiments of the invention are directed to an integrated circuit (IC) package assembly, including: one or more printed circuit boards (PCBs); and a set of chip packages, each including: an overmold; and an IC chip, overmolded in the overmold, and wherein: the chip packages are stacked transversely to an average plane of each of the chip packages, thereby forming a stack wherein a main surface of one of the chip packages faces a main surface of another one of the chip packages; and each of the chip packages is laterally soldered to one or more of said one or more PCBs and arranged transversally to each of said one or more PCBs, whereby an average plane of each of said one or more PCBs extends transversely to the average plane of each of the chip packages of the stack. Further embodiments are directed to related devices and fabrication methods.Type: ApplicationFiled: July 11, 2016Publication date: January 11, 2018Inventors: Thomas J. BRUNSCHWILER, Andreas Christian DOERING, Ronald Peter LUIJTEN, Stefano Sergio OGGIONI, Patricia Maria SAGMEISTER, Martin Leo SCHMATZ
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Patent number: 7948888Abstract: A network device including at least one rate-limited-queue and multiple timer modules, the network device being operable to receive and/or transmit data flows from and/or to a communication network. Each data flow includes multiple data packets. The network device being further operable to limit the predetermined transmission rate of the respective data flow dependent on whether a data congestion in the communication network has been indicated, in such a way, that in case of an indicated congested communication network a respective timer module is associated to each of the data flows and/or each group of data flows, whereas the data packets of the respective data flows and/or group of data flows are buffered in the rate-limited-queue. Each data packet in the rate-limited-queue is transmitted with a limited transmission rate predetermined by the respectively associated timer module when the data packet is at the head of the rate-limited-queue.Type: GrantFiled: December 4, 2008Date of Patent: May 24, 2011Assignee: International Business Machines CorporationInventors: Mircea Gusat, Ronald Peter Luijten, Cyriel Johan Minkenberg
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Publication number: 20090147679Abstract: A network device including at least one rate-limited-queue and multiple timer modules, the network device being operable to receive and/or transmit data flows from and/or to a communication network. Each data flow includes multiple data packets. The network device being further operable to limit the predetermined transmission rate of the respective data flow dependent on whether a data congestion in the communication network has been indicated, in such a way, that in case of an indicated congested communication network a respective timer module is associated to each of the data flows and/or each group of data flows, whereas the data packets of the respective data flows and/or group of data flows are buffered in the rate-limited-queue. Each data packet in the rate-limited-queue is transmitted with a limited transmission rate predetermined by the respectively associated timer module when the data packet is at the head of the rate-limited-queue.Type: ApplicationFiled: December 4, 2008Publication date: June 11, 2009Inventors: Mircea Gusat, Ronald Peter Luijten, Cyriel Johan Minkenberg
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Patent number: 7269158Abstract: Apparatus and method of operating a crossbar switch (1) having a control logic, an output port scheduler (2), n input ports (i—0, . . . , i—31) and m output ports (o—0, . . . , o—31), wherein information packets are routed from said n input ports to said m output ports, and wherein said output port scheduler (2) controls the sequence of packets output at said output ports (o—0, . . . , o—31). To ensure fairness regarding packet transfer/routing and the packet sequence, an input port number corresponding to the input port a new information packet is arriving at is stored in round-robin mode in a port number buffer (pnb—0). For output, said input port number is retrieved from said port number buffer (pnb—0) in round robin mode, too, and with this port number, address information regarding the packet is obtained from a control logic buffer of the crossbar switch (1).Type: GrantFiled: March 3, 2003Date of Patent: September 11, 2007Assignee: International Business Machines CorporationInventors: Abel Francois, Bernd Leppla, Ronald Peter Luijten, Norbert Schumacher
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Patent number: 7206308Abstract: Method and apparatus for providing a non-blocking routing network for establishing arbitrary connections between n primary nodes (m—0, . . . , m_n?1) and N?n secondary nodes (r—0, . . . , r_N?1). The routing network requires less physical connections than a corresponding Clos routing network while having small transmission delays. One embodiment of the invention provides a routing network that is well suited for direct on-chip implementation due to the matrix structure of the routing network.Type: GrantFiled: November 8, 2002Date of Patent: April 17, 2007Assignee: International Business Machines CorporationInventors: Juergen Koehl, Ronald Peter Luijten
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Publication number: 20040047334Abstract: Apparatus and method of operating a crossbar switch (1) having a control logic, an output port scheduler (2), n input ports (i—0, . . . , i—31) and m output ports (o—0, . . . , o—31), wherein information packets are routed from said n input ports to said m output ports, and wherein said output port scheduler (2) controls the sequence of packets output at said output ports (o—0, . . . , o—31). To ensure fairness regarding packet transfer/routing and the packet sequence, an input port number corresponding to the input port a new information packet is arriving at is stored in round-robin mode in a port number buffer (pnb—0). For output, said input port number is retrieved from said port number buffer (pnb—0) in round robin mode, too, and with this port number, address information regarding the packet is obtained from a control logic buffer of the crossbar switch (1).Type: ApplicationFiled: March 3, 2003Publication date: March 11, 2004Applicant: International Business Machines CorporationInventors: Abel Francois, Bernd Leppla, Ronald Peter Luijten, Norbert Schumacher
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Publication number: 20030117947Abstract: Method and apparatus for providing a non-blocking routing network for establishing arbitrary connections between n primary nodes (m_0, . . . , m_n−1) and N≧n secondary nodes (r_0, . . . , r_N−1). The routing network requires less physical connections than a corresponding Clos routing network while having small transmission delays. One embodiment of the invention provides a routing network that is well suited for direct on-chip implementation due to the matrix structure of the routing network.Type: ApplicationFiled: November 8, 2002Publication date: June 26, 2003Applicant: International Business Machines CorporationInventors: Juergen Koehl, Ronald Peter Luijten