Abstract: A device for determining speeds of a digital signal in a serial transmission line. The device comprises a first and second counter and a logic circuit. The first counter is adapted to count the duration of a first pulse in a first byte of the digital signal in the transmission line. The second counter is adapted to count the duration of a second pulse in the first byte. The logic circuit is coupled to the first and second counters. The logic circuit is adapted to compare the smallest duration of the first and second pulses with a plurality of pulse duration's of known baud rates to determine the baud rate of the digital signal in the transmission line.

Abstract: A circuit that uses a bi-directional buffer as follows: First a tri-state output buffer is connected to a functional clock and a bi-directional port is connected to a test clock. The bi-directional buffer is configured to receive control signals to selectively block and unblock the tri-state output port connected to the functional clock. In addition, the bi-directional port connected to a test clock is connected to the internal logic of the device. When the tri-state output buffer connected to the functional clock is blocked, the test clock transmits a clock signal to the internal logic of the device. When the tri-state output buffer connected to the functional clock is unblocked, the functional clock transmits a clock signal to the internal logic of the device.

Abstract: A method and system for performing simultaneous tests and avoiding task collisions using a hardware description language includes designating a timeslot for one or more of the simultaneous tests, associating the designated timeslot with one or more of the tasks to be performed in a test, determining if the designated timeslot is available before executing the tasks associated with timeslots and executing the tasks when the designated timeslots become available.

Abstract: A method and system for performing simultaneous tests and avoiding task collisions using a hardware description language includes designating a timeslot for one or more of the simultaneous tests, associating the designated timeslot with one or more of the tasks to be performed in a test, determining if the designated timeslot is available before executing the tasks associated with timeslots and executing the tasks when the designated timeslots become available.

Abstract: A device for determining speeds of a digital signal in a serial transmission line. The device comprises a first and second counter and a logic circuit. The first counter is adapted to count the duration of a first pulse in a first byte of the digital signal in the transmission line. The second counter is adapted to count the duration of a second pulse in the first byte. The logic circuit is coupled to the first and second counters. The logic circuit is adapted to compare the smallest duration of the first and second pulses with a plurality of pulse duration's of known baud rates to determine the baud rate of the digital signal in the transmission line.

Abstract: A circuit that uses a bi-directional buffer as follows: First a tri-state output buffer is connected to a functional clock and a bi-directional port is connected to a test clock. The bi-directional buffer is configured to receive control signals to selectively block and unblock the tri-state output port connected to the functional clock. In addition, the bi-directional port connected to a test clock is connected to the internal logic of the device. When the tri-state output buffer connected to the functional clock is blocked, the test clock transmits a clock signal to the internal logic of the device. When the tri-state output buffer connected to the functional clock is unblocked, the functional clock transmits a clock signal to the internal logic of the device.