Abstract: A chip carrier socket 2 comprises, a chip carrier receiving member, multiple electrical terminals 4 extending over component mounting pads 64 of a substrate 10, and surface mount contacts 62 of the terminals 4 being aligned so as to engage the conductive mounting pads 64 that are in alignment with conductive leads 6 of a chip carrier 8, whereby the same mounting pads 64 can be used for surface mount attachment to the leads 6, and can be used for surface mount attachment to the terminals 4 of the chip carrier socket 2. The terminals include recesses 66 on edges adjacent to the surface mount contacts to prevent these edges from being wetted by solder. Certain ones of the terminals include posts 38 to uniquely orient the socket 2 with respect to the substrate 10.