Abstract: Organic light emitting diodes having a transparent cathode structure is disclosed. The structure consists of a low work function metal in direct contact with the electron transport layer of the OLED covered by a layer of a wide bandgap semiconductor. Calcium is the preferred metal because of its relatively high optical transmissivity for a metal and because of its proven ability to form a good electron injecting contact to organic materials. ZnSe, ZnS or an alloy of these materials are the preferred semiconductors because of their good conductivity parallel to the direction of light emission, their ability to protect the underlying low work function metal and organic films and their transparency to the emitted light. Arrays of these diodes, appropriately wired, can be used to make a self-emissive display. When fabricated on a transparent substrate, such a display is at least partially transparent making it useful for heads-up display applications in airplanes and automobiles.

Abstract: An apparatus for testing for and classifying defects in a TFT/LCD array having gate lines and data lines. Devices are provided for activating cells of the array by applying gate pulses to the gate lines and pulses to the data lines. Devices are also provided for acquiring waveforms from data lines of the array. Additional devices sample the waveforms at selected points in time. A computer may be used to classify the waveforms to indicate whether defects are present and if present, the nature of the defects by comparing voltages of the waveform at the selected points in time.

Abstract: A charge pumping structure is disclosed for use in a substrate bias voltage generator. It includes a capacitor on a substrate region for coupling to a first node periodic voltage signals received at a second node. A first diode structure provides a current path from the first node to the substrate and a second diode structure provides a current path between the first node and a reference potential, which is typically the ground. The first diode structure includes a PN junction diode, an isolation ring for collecting minority charge carriers injected into the substrate and is constructed on a portion of the substrate that has a lower doping concentration than the underlying substrate portion establishing a built-in electric field which inhibits the flow of minority carriers from the first diode to the underlying substrate.

Abstract: Disclosed is an overvoltage protection structure which when used with CMOS circuits it protects them from overvoltage conditions while minimizing latch-up conditions in the structure. It consists of a well region of an opposite conductivity to that of the substrate defining a pocket region having a conductivity type which is similar to that of the substrate. A first PN junction diode is formed in a portion of the well region and a second PN junction diode is formed in the pocket region. The two diodes have opposite polarity and they both are connected to a signal line in such a way that one of the two diodes will be forward biased if the voltage on the signal line exceeds the bounds of the power supply voltages. The pocket region is connected to a V.sub.SS terminal which is normally grounded and the well region is connected to a power supply V.sub.DD.

Abstract: A process for making a CMOS dual-well semiconductor structure with field isolation doping, wherein only a single lithographic masking step is required for providing self-alignment both of the wells to each other and also of the field isolation doping regions to the wells. The lithographic masking step forms a well mask and defines an oxidation barrier which acts as: an implant mask (absorber) during the ion-implantation of a field dopant of one type; an oxidation barrier over one well during the oxidation of the opposite-type well to form over the one well a sacrificial oxide layer which forms the alignment marks for subsequent formation of the field-doping regions; and a dopant-transmitter during the ion-implantation of an opposite-type field dopant which is simultaneously absorbed by the sacrificial oxide. As a result, there are formed field-doped oxide layers self-aligned to the wells so that, with a subsequent masking step, oxide field isolations are defined over the doped oxide layers.

Abstract: A method is disclosed for fabricating series and/or parallel connected P channel and N channel FET device topologically connected in a CMOS configuration, where the individual FET devices share a common gate sandwiched between them, forming a five terminal device. A new device structure and complementary MOSFET circuitry is also disclosed. The disclosed process produces devices and circuits which overcome the main disadvantage of prior art CMOS transistors, namely excessive area consumption and parasitic effects.

Abstract: A CMOS driver or pull up circuit is provided which includes a pull up transistor of a given conductivity type and a precharged bootstrap capacitor which discharges fully through a second transistor having a conductivity type opposite to that of the pull up transistor to the control gate or electrode of the pull up transistor. A third transistor may be used to initiate discharge by providing power supply voltage to the control gate of the pull up transistor.

Abstract: A method is disclosed for fabricating series and/or parallel connected P channel and N channel FET device topologically connected in a CMOS configuration, where the individual FET devices share a common gate sandwiched between them, forming a five terminal device. A new device structure and complementary MOSFET circuitry is also disclosed. The disclosed process produces devices and circuits which overcome the main disadvantage of prior art CMOS transistors, namely excessive area consumption and parasitic effects.

Abstract: A simple process is provided which forms a bulk CMOS structure by depositing a layer of material which resists oxidation, e.g., a barrier layer of silicon nitride on an N- semiconductor substrate, forming a P well in the substrate through a given segment of the barrier layer, removing a first segment of the barrier layer to form N+ regions for N channel source and drain and N- substrate contact, removing a second segment of the barrier layer to form a P+ field region, removing a third segment of the barrier layer to form P+ regions for source and drain of a P channel device, forming a first control electrode having a given work function for the P channel device which acts as an ion barrier and then forming a second control electrode between the N channel source and drain regions having a work function different from that of the first control electrode.

Abstract: A memory system is provided wherein extended injection-limited programming techniques attain a substantially uniform programming behavior from an ensemble of fabricated devices or cells to provide the maximum obtainable voltage threshold shift within a minimum time period. In order to produce these desired results, a floating gate of a device is charged by applying to the control gate of the device a first voltage during a portion of this time period which produces an accelerating field in a dielectric layer disposed adjacent to the floating gate and then applying to the control gate during the remaining portion of this time period a second voltage of greater magnitude than that of the first voltage prior to or when the accumulation of charge on the floating gate causes a retarding field to be established in the dielectric layer.

Abstract: A method is provided for making complementary field effect transistors in a semiconductor layer having a first portion including an N type transistor with a channel region defined by N+ source and drain regions and having a second portion including a P type transistor with a channel region defined by P+ source and drain regions. An insulating layer is disposed over the first and second portions with thin insulating films formed over the channel regions.

Abstract: This teaches that by measuring the rate of change in gate current of an insulating gate field effect transistor, under normal operating conditions, the time required to achieve a predetermined change in source-to-drain current in the transistor can be found. Because changes in gate current depends more on sensitivity on charge trapping in the oxide than do changes in channel current, and since the gate current occurs only in the small region of electron emission, the effects on gate current are more quickly developed than the secondary effect of reduced channel current due to the charge in gate oxide caused by the presence of trapped electrons.