Patents by Inventor Ronald Rathbone

Ronald Rathbone has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230338608
    Abstract: A dressing comprises a delivery vehicle and platelet lysate. The dressing can also include an antimicrobial agent, a hemostatic agent, and a binder. It is contemplated that the dressing can be used for expediting hemostasis, improving antimicrobial activity, minimizing fluid loss, and accelerating wound healing when applied to a wound. The dressing would be useful in applications including military in-theater medical care and for conditions such as diabetic foot ulcers, as well as other applications.
    Type: Application
    Filed: May 26, 2023
    Publication date: October 26, 2023
    Inventors: Vivek Prabhakar Raut, Meghan Elizabeth Samberg, Kolby Luke Day, Brian Roy Barnes, Christopher Ronald Rathbone, Patrick Patterson, Donald Jude Brown, Justin Jeffrey Baker
  • Publication number: 20190134252
    Abstract: A dressing comprises a delivery vehicle and platelet lysate. The dressing can also include an antimicrobial agent, a hemostatic agent, and a binder. It is contemplated that the dressing can be used for expediting hemostasis, improving antimicrobial activity, minimizing fluid loss, and accelerating wound healing when applied to a wound. The dressing would be useful in applications including military in-theater medical care and for conditions such as diabetic foot ulcers, as well as other applications.
    Type: Application
    Filed: December 28, 2018
    Publication date: May 9, 2019
    Inventors: Vivek Prabhakar Raut, Meghan Elizabeth Samberg, Kolby Luke Day, Brian Roy Barnes, Christopher Ronald Rathbone, Patrick Patterson, Donald Jude Brown, Justin Jeffrey Baker
  • Patent number: 4323913
    Abstract: An integrated semiconductor circuit arrangement is provided which comprises a substrate of semiconductor material of one conductivity type, an epitaxial layer of the opposite conductivity type formed on one major surface of the substrate, the epitaxial layer having function elements such as transistors, diodes, resistances, and so forth, formed therein. A least some of these function elements are located in insulated regions provided for them which in the boundary area between the substrate and the epitaxial layer are bounded by a pn junction and which at right angles to this boundary area are bounded by oxide walls which extend through the epitaxial layer to the substrate. The oxide walls are surrounded by a resistor region of the said one conductivity type which extends through the epitaxial layer to the substrate.
    Type: Grant
    Filed: October 17, 1979
    Date of Patent: April 6, 1982
    Assignee: Siemens Aktiengesellschaft
    Inventors: Helmuth Murrmann, Ronald Rathbone, Ulrich Schwabe
  • Patent number: 4143455
    Abstract: Semiconductor components, as for LSI-circuits are produced in such a manner that epitaxial layers as well as buried layers are dispensed with while an increased manufacturing yield and an increased structural packing density is achieved via an oxide insulating technique. The process involves applying and structuring a first insulating layer, such as composed of Si.sub.3 N.sub.4, onto a semiconductor substrate having a first zone of one conductivity type therein, etching insulating grooves into the substrate areas not covered with the first insulating layer and filling such grooves with a second insulating layer, such as composed of SiO.sub.2, which is thicker than the first insulating layer, and then emplacing the various semiconductor structures at select surface areas between spaced-apart areas of the second insulating layer so as to complete the semiconductor structure.
    Type: Grant
    Filed: July 3, 1978
    Date of Patent: March 13, 1979
    Assignee: Siemens Aktiengesellschaft
    Inventors: Ulrich Schwabe, Ronald Rathbone
  • Patent number: 4110779
    Abstract: A high-frequency transistor is provided having a small effective emitter width and a low base bulk resistance. The transistor is isolated from adjacent components by insulating material portions. The base zone comprises first and second doped zones. The first zone establishes the effective emitter width and has a lower concentration than the second zone. The lateral extent of the first zone is established by one of the insulating material portions and the second zone of the base zone. The collector of the transistor is positioned beneath both the first and second zones of the base zone and the emitter of the transistor is positioned above the first zone and an end portion of the second zone.
    Type: Grant
    Filed: December 13, 1976
    Date of Patent: August 29, 1978
    Assignee: Siemens Aktiengesellschaft
    Inventors: Ronald Rathbone, Ulrich Schwabe
  • Patent number: 4048517
    Abstract: A logic element, particularly a bipolar gate circuit for an LSI-circuit, employing a pair of Schottky-diodes, a pair of resistances and a transistor, with the diodes, connected in high resistance direction, to respective inputs, the other sides of the diodes being connected in common to a first resistance and to the base of the transistor, with said first resistance being operatively connected to a reference potential, said second resistance connecting the collector of the transistor, and the common connection of said diodes.
    Type: Grant
    Filed: June 28, 1976
    Date of Patent: September 13, 1977
    Assignee: Siemens Aktiengesellschaft
    Inventors: Ronald Rathbone, Peter Rydval