Abstract: A secure processor arrangement for a communications secure kernel of a secure processor system. This processor arrangement provides protection of plain text data and suitable isolation of data necessary to support single processor architecture. A red memory subsystem stores plain text data and a black memory subsystem stores cypher text data. In order to prevent mishandling of plain text data, the single processor is allowed to directly read and to write red memory, but the single processor is only permitted to directly read from the black memory.

Abstract: The present invention consists of a hardware simulator with bus evaluator logic for use in simulating and fault grading of very large scale digital circuits containing buses. In this invention the status of a bus is continously upgraded each time a primitive is evaluated that has an output coupled to the bus. As bus driver primitives are evaluated, the state of the bus is determined on the fly and stored in an accumulator register, called the bus register. Evaluation of the bus continues using the data stored in the bus register and the state of each driver until all drivers have been evaluated. After the last bus driver is evaluated the state of the bus is known and the bus primitive is assigned the value, or state, stored in the bus register hardware and is passed to all receivers on the bus.