Abstract: A single layer capacitor can include a substrate having a first surface and a second surface opposite the first surface. A resistive layer can be formed over at least a portion of the first surface of the substrate. A first conductive layer can be formed over at least a portion of the resistive layer. A second conductive layer can be formed over at least a portion of the second surface of the substrate. As such, the single layer capacitor can include a resistor and a capacitor formed in series with one another.

Abstract: A metal-oxide-semiconductor (MOS) capacitor can include a substrate comprising a semiconductor material, an oxide layer formed over a first surface of the substrate, a resistive layer formed over at least a portion of the oxide layer, and a conductive layer formed over at least a portion of the resistive layer. As such, the MOS capacitor can include a resistor and a capacitor formed in series with one another.

Abstract: A component array can include a first multilayer ceramic component having a first terminal at a first end and a second terminal at a second end opposite the first end in a first direction. A second component can have a first terminal at a first end and a second terminal at a second end opposite the first end in the first direction. A heat sink layer can be arranged between the first component and the second component in a second direction that is perpendicular to the first direction. The heat sink layer can include a first metallization layer electrically connecting the first terminal of the first multilayer ceramic component with the first terminal of the second multilayer ceramic component and a second metallization layer electrically connecting the second terminal of the first multilayer ceramic component with the second terminal of the second multilayer ceramic component.

Abstract: A component array can include a first multilayer ceramic component having a first terminal at a first end and a second terminal at a second end opposite the first end in a first direction. A second component can have a first terminal at a first end and a second terminal at a second end opposite the first end in the first direction. A heat sink layer can be arranged between the first component and the second component in a second direction that is perpendicular to the first direction. The heat sink layer can include a first metallization layer electrically connecting the first terminal of the first multilayer ceramic component with the first terminal of the second multilayer ceramic component and a second metallization layer electrically connecting the second terminal of the first multilayer ceramic component with the second terminal of the second multilayer ceramic component.

Abstract: A heat sink component can include a body including a thermally conductive material that is electrically non-conductive. At least one first terminal can be formed over a first end of the body. At least one second terminal formed over a second end of the body. The second end of the body can be opposite the first end of the body in an X-direction. The heat sink component can have a length in the X-direction and a width in a Y-direction that is parallel with the top surface and perpendicular to the X-direction. A ratio of the width to the length can be greater than about 1.

Abstract: A component array can include a first multilayer ceramic component having a first terminal at a first end and a second terminal at a second end opposite the first end in a first direction. A second component can have a first terminal at a first end and a second terminal at a second end opposite the first end in the first direction. A heat sink layer can be arranged between the first component and the second component in a second direction that is perpendicular to the first direction. The heat sink layer can include a first metallization layer electrically connecting the first terminal of the first multilayer ceramic component with the first terminal of the second multilayer ceramic component and a second metallization layer electrically connecting the second terminal of the first multilayer ceramic component with the second terminal of the second multilayer ceramic component.

Abstract: An element array and a footprint layout for an element array are disclosed. The element array can have a rectangular configuration defining two side surfaces and two end surfaces. The element array can include a plurality of stacked dielectric-electrode layers. One dielectric-electrode layer can include a plurality of element electrodes, such as eight element electrodes. Each of the plurality of element electrodes forms a part of an individual element for the element array. The element array device can further include a common electrode. The common electrode is used as part of each of the individual elements for the element array. The common electrode can include a lead for termination to one of the two end surfaces of the element array or, in a particular embodiment, to one of the two side surfaces of the element array.

Abstract: An element array and a footprint layout for an element array are disclosed. The element array can have a rectangular configuration defining two side surfaces and two end surfaces. The element array can include a plurality of stacked dielectric-electrode layers. One dielectric-electrode layer can include a plurality of element electrodes, such as eight element electrodes. Each of the plurality of element electrodes forms a part of an individual element for the element array. The element array device can further include a common electrode. The common electrode is used as part of each of the individual elements for the element array. The common electrode can include a lead for termination to one of the two end surfaces of the element array or, in a particular embodiment, to one of the two side surfaces of the element array.

Abstract: The present subject matter is directed to methods and apparatus for providing a multilayer array component with interdigitated electrode layer portions configured to selectively provide signal filtering characteristics, over-voltage transient suppression capabilities, and land grid array (LGA) terminations. Embodiments of the present subject matter may define a single capacitor, a capacitor array, or a multilayer vertically integrated array with configurable equivalent electrical characteristics including equivalent series inductance (ESL), equivalent series resistance (ESR), and configurable capacitance and voltage clamping and transient suppression capabilities.