Abstract: A rotating mirror digital streak camera including means to convert an image presented to a roughly cylindrical image plane into a plurality of discrete zones, a sensor being adapted to capture the image data associated with each such zone, and a means to assemble the collected data to reconstruct the original image that is swept across the image plane as an essentially uninterrupted image.

Abstract: A network synchronization method designed to provide synchronization of multiple networks and devices. This invention provides a specific method for determining which nodes are responsible for network synchronization as nodes fail or cannot see each other due to conditions on the network. This allows for fault tolerance in a network in which conditions change dynamically. In addition, this invention uses synchronization codes and network numbers to isolate separate networks using the same physical medium, thus allowing sharing of network resources.

Abstract: A method and system for providing low cost narrow band digital power line communication using OFDM-like protocols to promote spectral diversity, reduce data loss, and provide higher data throughput. This invention provides a specific design to accommodate the requirements of a wide variety of communication applications and is adapted to make use of an AC power line communication within a building or facility without requiring dedicated hard wiring and does so with the advantages of OFDM but without the high costs of OFDM.

Abstract: A demodulator for demodulating clear mode waveforms such as Phase Shift Keyed and Quadrature Amplitude Modulated waveforms, is capable of demodulating signals with much greater data rates than the clock rate of the device in which the demodulator resides by converting serial input samples into vectors. The input vectors are converted to “soft-decision” (data estimate) vectors which are input to a parallel-to-serial multiplexer, and the vector elements are output serially at the symbol clock rate to represent demodulated data. In the preferred embodiment, the vector demodulator at least includes a preprocessor, a digital phase shifter, and a symbol demodulator which, inter alia, outputs a phase rotator command signal to control the carrier recover phase rotation process in the digital phase shifter.

Abstract: A system for providing communications between a wide variety of communication devices using the AC power line within a building or facility without requiring dedicated hard wiring. This invention is designed specifically to accommodate such devices as gateways, PCs, telephone devices, RF equipment, home automation devices and audio-visual devices.

Abstract: An integrated circuit includes a reconfigurable FIR filter has an input port for receiving digital input signals and an output coupled to a coherent signal processor and a coherent memory. The FIR filter programmably provides filtered signals to the coherent signal processor for storage in the coherent memory. The integrated circuit further includes a sequential weight processor having an input coupled to an output of the coherent memory. The sequential weight processor includes a weight memory and operates to output symbol soft decision data resulting from processing the digital input signals. The integrated circuit is programmable into one of a plurality of operating modes, including at least one of a received signal acquisition mode, a channel estimator mode, an adaptive equalizer mode, and a channel-wise differential mode.

Abstract: An integrated circuit includes a reconfigurable FIR filter has an input port for receiving digital input signals and an output coupled to a coherent signal processor and a coherent memory. The FIR filter programmably provides filtered signals to the coherent signal processor for storage in the coherent memory. The integrated circuit further includes a sequential weight processor having an input coupled to an output of the coherent memory. The sequential weight processor includes a weight memory and operates to output symbol soft decision data resulting from processing the digital input signals. The integrated circuit is programmable into one of a plurality of operating modes, including at least one of a received signal acquisition mode, a channel estimator mode, an adaptive equalizer mode, and a channel-wise differential mode.

Abstract: An integrated circuit includes a reconfigurable FIR filter has an input port for receiving digital input signals and an output coupled to a coherent signal processor and a coherent memory. The FIR filter programmably provides filtered signals to the coherent signal processor for storage in the coherent memory. The integrated circuit further includes a sequential weight processor having an input coupled to an output of the coherent memory. The sequential weight processor includes a weight memory and operates to output symbol soft decision data resulting from processing the digital input signals. The integrated circuit is programmable into one of a plurality of operating modes, including at least one of a received signal acquisition mode, a channel estimator mode, an adaptive equalizer mode, and a channel-wise differential mode.

Abstract: A detector circuit for indicating the chip rate of a direct sequence frequency hopped data transmission signal. The wide band input signal is channelized into L adjacent sub-bands and each sub-band signal is multiplied by a delayed copy of itself and then hard limited, after which all the hard limited product signals are totalized to give a resultant signal representative of the chip rate.

Abstract: A signal detector for receiving a wide band (W) of frequency-hopped signals which channelizes the incoming signals, via filter banks into a plurality (L) of channels. Magnitude squaring circuits in each channel generate a "power" estimate which is compared to a preset threshold value by threshold-quantizer units that produce a positive voltage (=1) if the threshold is exceeded. After summation of all the channels, the direct sequence (DS) signal component and noise component are processed so that a DC voltage is produced if a frequency-hop signal (FH) is present which is greater in value than when the signal is not present. Thus the DC signal indicates whether the FH signal is present or absent.

Abstract: A hop rate detector, for receiving frequency-hopped signals carrying information data, which generates a tone at the "hop rate" when modulated or unmodulated frequency-hopped signals are present. The input signal is channelized into sub-bands via filter banks and the signal in each channel is power detected (squared) and compared to a present threshold to produce a positive voltage (="1") if the threshold is exceeded and zero volts (="0") otherwise. The channel signals are split into an upper band (B.sub.u) and lower band (B.sub.d), then each band is summed and the lower band sum subtracted from the upper band sum to provide a first stage signal. The first stage signal has its DC component removed, then is multiplied by a delayed copy of itself to provide a frequency tone indicating the hop rate of the received signal.

Abstract: Adaptive filters are used to separate frequency hop signals to improve the detection and estimation of the frequency hop signals. In preferred embodiments, two or more adaptive filters (which can be connected in series or in parallel) exhibit different convergence characteristics to isolate a frequency hop signal.