Abstract: An instruction processing circuit comprises an instruction decoder (120, 121, 122), with an instruction input coupled to an instruction source (10) and a control output coupled to the control input of an execution circuit (124). The instruction decoder (120, 121, 122) comprises a plurality a predecoding circuit (120) with an input coupled to the instruction input and outputs coupled to control inputs of freezing circuits (121), which feed respective parallel sub-decoders 122. The predecoding circuit (120) detects to which type of instruction a supplied instruction belongs, and controls, dependent on the detected type, to which of the sub-decoding circuits (122) instruction information derived from the supplied instruction will be passed and to which of the sub-decoding circuits (122) supply of instruction information derived from a previously supplied instruction will be frozen.