Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to a package that includes multiple PICs in the package that are optically coupled with each other. In embodiments, the package may include discrete electronic and optical components, and thermal management solutions for co-packaging of multiple PICs. Other embodiments may be described and/or claimed.

Abstract: Example techniques to enable a flip chip underfill exclusion zone include use of bump barriers, films or etched substrate cavities to prevent underfill from reaching the flip chip underfill exclusion zone.

Abstract: Logic and memory may be packaged together in a single integrated circuit package that, in some embodiments, has high input/output pin count and low stack height. In some embodiments, the logic may be stacked on top of the memory which may be stacked on a flex substrate. Such a substrate may accommodate a multilayer interconnection system which facilitates high pin count and low package height. In some embodiments, the package may be wired so that the memory may only be accessed through the logic.

Abstract: A device includes a folded flex substrate. A memory die is connected to a first side of the folded flex substrate. A logic die is connected to a second side of the folded flex substrate. A trace routing pattern of source voltage signals is identical to a trace routing pattern of collector voltage signals.

Abstract: In one embodiment, a package-to-package stack is assembled comprising a first integrated circuit package, and a second integrated circuit package which are mechanically and electrically connected using an interposer and a substrate folded around the interposer. Other embodiments are described and claimed.

Abstract: A flip-chip is mounted on a flex substrate. A flip-chip is mounted on a flex substrate, and a wire-bond chip is mounted on the flip-chip. A packaged flip-chip die is coupled to the flex substrate. A computing system is also disclosed that includes the flip-chip on a flex substrate configuration.

Abstract: A wire-bonding substrate includes in-line wire bonds that are substantially of the same pitch on the die bond pads as on the substrate bond pads. A wire-bonding substrate also includes staggered bond pads on at least one of the die and the substrate. A substrate bond pad includes a first wire-bond pad and a first via that is disposed directly below the first wire-bond pad in the wire-bonding substrate. A package is also disclosed that includes a die that is coupled to the first wire-bonding pad. A computing system is also disclosed that includes the in-line wire-bonding configuration.

Abstract: A microelectronic assembly is provided, having redistribution conductors that are formed over a microelectronic die of the assembly instead of through a substrate to which the microelectronic die is mounted. A redistribution conductor is formed by a pair of contacts on the die and a conductive portion connecting the contacts to one another. A wirebonding wire is attached to each contact. One of the wirebonding wires may be used to connect to a terminal on the substrate, a terminal on another die, or to another contact on the same die.

Abstract: Buildup layers may be formed over a flexible substrate. A suitable cavity may be formed in the buildup layers and a silicon die may be positioned over the flexible substrate on a die attach formed within the cavity. As a result, a lower profile flexible substrate package is possible.