Abstract: A method to join a first enclosed workpiece and a second enclosed workpiece is provided. The first enclosed workpiece includes a first connecting end and a first cavity region. The second enclosed workpiece includes a second connecting end and a second cavity region. A backing member is placed in the first connecting end, with a first end within the first cavity region. A resilient member is positioned in the first cavity region, with a first portion within the first cavity region. The second enclosed workpiece is positioned proximal to the first enclosed workpiece to define a gap between the first connecting end and the second connecting end. Upon positioning, a second end of the backing member and a second portion of the resilient member are placed within the second cavity region. The first connecting end is then welded with the second connecting end over the backing member near the gap.

Abstract: A row driver circuit receives a first supply voltage and a second supply voltage. The circuit provides the first supply voltage on an output responsive to the first supply voltage being greater than a threshold value. The circuit generates a boosted voltage that is greater than the first supply voltage and provides that boosted voltage on the output responsive to the first supply voltage being less than the threshold value.

Abstract: A memory system 20 includes a first array 100 and a second array 102 of memory cells. The memory system allows for a quick transfer of the contents of one of the arrays with another one of the arrays. Through the use of a transfer gate (128) interposed between column decoders (150 and 152) corresponding to the two memory arrays, data may be transferred between the two arrays in a single timing cycle. Furthermore, even given the interconnection between the two memory arrays due to the transfer gate, the two memory arrays can be operated independently of one another, with respect to address, data, and timing information.

Abstract: A processing system 100 is disclosed which includes a system master 101, a system bus 102 coupled to the master, and a plurality of bus interface circuits 106 coupled to bus 102. A first one of the bus interfaces 106 includes a mapping signal input coupled to the master and a mapping signal output, the first bus interface 106 operable to latch-in at least one first selected address bit presented by the master on the system bus in response to a mapping enable signal received at the mapping signal input from the master 101. A second bus interface 106 is provided coupled to the bus 102 and having a mapping signal input coupled to the mapping signal output of first bus interface 106, the second bus interface 106 operable to latch-in at least one second selected address bit presented by the master 101 on the bus 102 in response to a second mapping enable signal received at the mapping input of the second bus interface 106 from the first bus interface 106.

Abstract: An information processing system 400 includes a subsystem 402 having a processing resource 404 and a bus interface 403. An active logic mapping signal is presented to a mapping input bus interface 403. The system also includes a master processing device which is operable to write at least some bits of a starting address into bus interface 403, determine an ending address for subsystem 402 and lock subsystem 402.

Abstract: A processing system 100 is disclosed which includes a system master 101, a system bus 102 coupled to the master, and a plurality of bus interface circuits 106 coupled to bus 102. A first one of the bus interfaces 106 includes a mapping signal input coupled to the master and a mapping signal output, the first bus interface 106 operable to latch-in at least one first selected address bit presented by the master on the system bus in response to a mapping enable signal received at the mapping signal input from the master 101. A second bus interface 106 is provided coupled to the bus 102 and having a mapping signal input coupled to the mapping signal output of first bus interface 106, the second bus interface 106 operable to latch-in at least one second selected address bit presented by the master 101 on the bus 102 in response to a second mapping enable signal received at the mapping input of the second bus interface 106 from the first bus interface 106.

Abstract: A display control system (200) for transferring video and graphical data processed in a first processing device (201) having a dedicated display screen to a second processing device (202) for display on the screen (152) of a conventional television set (150). The first processing device (201) and the second processing device (202) communicate by means of a pair of optical driver/receivers (203, 207). The second processing device (202) captures selected frames from a broadcast television picture displayed on the screen (152) of the television (150) and transmits the captured frames to the first processing device (201) for storage or display on the dedicated display screen.

Abstract: A pre-combustion chamber assembly and method for an internal combustion engine consists of first, second and third body portions of different metallic materials. A second end of the first body portion is joined to the first end of the second body portion by brazing and the first end of the third body portion is joined to the second end of the second body portion by controlled depth penetration welding. The first, second and third body portions are pre-machined. The first and second body portions are connected to form a first subassembly and the third body portion is subsequently connected to the first subassembly.

Abstract: A sense amplifier sensing data on a pair of complimentary half-bitlines 301a, 301b connected to a static random access memory cell 300. First and second sensing transistors 405a, 405b amplify a voltage difference between first and second half-bitlines 301 during an active cycle. First and second restore transistors 404a, 404b pull the first and second half-bitlines to corresponding first and second voltage rails in response to the amplified voltage difference. SR Latch 406, 407 retains data from cycle to cycle.

Abstract: A system is provided for transferring information across a conductor 203. Transmitting circuitry 210 receives information in the form of a first signal having a first voltage swing and, in response, outputs a second signal having a second voltage swing. The first voltage swing is between a first high voltage and a first low voltage and the second voltage swing is between a second high voltage less than the first high voltage and a second low voltage greater than the first low voltage. The second high voltage is substantially equal to a voltage level of a first voltage rail to which the transmitting circuitry 210 is coupled and the second low voltage is substantially equal to a voltage level of a second voltage rail to which the transmitting circuitry 210 is coupled. The conductor 203 carries the second signal output from the transmitting circuitry 210.

Abstract: A memory 20 includes a first array 100 and a second array 102 of memory cells. A first data port 118 allows for the exchange of data with the first array 100 and a second data port 120 allows for the exchange of data with the second array 102. Memory system 20 also includes a circuitry 122 for controlling data exchanges in a selected mode with the first array 100 via the first data port 118 and with the second array 102 via the second data port 120, the exchanges with the first and second arrays 100 and 102 being asynchronous.

Abstract: A memory 600 including an array of memory cells 201 and a plurality of input/output terminals 220 for receiving control bits during control cycles and accessing selected ones of the cells 201 during data access cycles. A command bit input terminal 221 is provided for receiving command bits for initiating the control cycles and a mapping input terminal 222 is provided for receiving a mapping enable signal to initiate a mapping mode. Circuitry 215/ 216 is provided for decoding control bits received during at least one control cycle occurring during a mapping mode for allowing a mapping of a set of addresses for accessing the cells of the array 201.

Abstract: A memory including a plurality of input/output terminals 220 for exchanging data bits during a data access cycle and receiving command and control bits during a command and control cycle. The memory further includes an array of memory cells 201, a data input/output circuitry for transferring data between the input/output terminals and the array of memory cells during the data access cycle, and control circuitry for controlling operations of the memory in response to command and control bits received at the input/output terminals during the command and control cycle.

Abstract: A system 500 is provided for transferring signals across a bus which includes a power source 550 operating between a high voltage rail at a first supply voltage level and a low voltage rail at a second supply voltage rail, power source 550 generating a third supply voltage level on an output thereto. The third supply voltage level is greater than the first supply voltage level. A processing circuitry 103, 104 is included for generating a plurality of data signals each having a first voltage swing between a first logic high level substantially equal to the first supply voltage level and a first logic low level substantially equal to the second supply voltage level. The system additionally includes a plurality of buffers, 520, each buffer 520 being coupled to the power source 550 output and receiving a selected one of the data signals.

Abstract: A fluid filter, such as an oil filter for example, has a canister, a top plate and a sealing ring. The sealing ring overlaps portions of the top plate and canister. The sealing ring and canister are joined one to the other by laser welding about the sealing ring adjacent the canister and forming a mechanical lock between the canister and the top plate by mixing of materials.

Abstract: A system 600 is provided having a line driver 202 for transmitting signals across a line 201 from a first processing circuit 601 to a second processing circuit 602. Line driver 202 receives an input signal from processing circuit 601 having a first voltage swing between a first high voltage level and a first low voltage level. Line driver 202 reduces power dissipation in line 201 by transmitting an output signal on line 201 having a second voltage swing between a second low voltage level greater than the first low voltage level and a second high voltage level less than the first high voltage level. System 600 also contains comparator 610 which receives the signal having the reduced second voltage swing and compares the received signal to a reference voltage. The output of comparator 610 restores the received signal to the full voltage swing of the input signal received by line driver 202 and transfers the restored signal to processing circuit 602.

Abstract: A line driver 202 is provided for transmitting signals across a line 201. Line driver 202 receives an input signal having a first voltage swing between a first high voltage level and a first low voltage level. Line driver 202 reduces power dissipation in line 201 by transmitting an output signal on line 201 having a second voltage swing between a second low voltage level greater than the first low voltage level and a second high voltage level less than the first high voltage level.

Abstract: A memory device 200 which includes a multiplexed address/data input/output 230. Circuitry 200 is based around an array 201 of memory cells and includes circuitry 202, 204 for addressing at least one of the cells in the array in response to at least one address bit and circuitry 208, 210, 211, 212 for exchanging data with an addressed one of the cells. Memory device 200 also includes control circuitry 206 operable to pass an address bit presented at the multiplexed input/output to the circuitry for addressing during a first time period and allow for the exchange of data between the circuitry for exchanging and multiplexed input/output during a second time period.

Abstract: A power fail control system for a CPU (10) and external memory (16) utilizes a controller (18). The controller (18) is operable to detect an early power fail situation and output an interrupt to the CPU (10). The CPU (10) then goes into a power down sequence and stores critical instructions in an internal memory array (30) constituting a hidden memory during the power down sequence. An out of tolerance detector detects when the power supply voltage has fallen below a predetermined threshold and then generates reset signal. The reset signal is input to the CPU (10) to indicate that no further instructions are executable. In addition, a Chip Enable switch (46) is operated to inhibit memory control signals from being transferred from the CPU (10) to the memory (16). The internal hidden memory (30) is also inhibited from having data written thereto in the presence of the reset signal. A backup battery (22) is provided which is connected to one side of a switch.

Abstract: High current capacity output drivers for digital devices have output noise reduced and more quickly achieve stability by the insertion of resistance in series with inherent, parasitic inductance. The resistance may be one or more fixed resistances formed in the same circuit as the drivers. The resistance may also include sensor devices that selectively increase the resistance of the output drivers in accordance with the voltage produced by the parasitic inductors. Both fixed resistances and sensor devices may be used together.