Patents by Inventor Ronald Todd

Ronald Todd has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7281875
    Abstract: A caulk applicator attachable to a caulk delivery apparatus. The caulk applicator comprises an applicator body having a retainer bracket and a scraper element, wherein the retainer bracket is attachable to the caulk delivery apparatus. An applicator wheel is rotatably mounted to the applicator body and has a fluid application surface, wherein the fluid application surface is engageable with the scraper element.
    Type: Grant
    Filed: January 25, 2007
    Date of Patent: October 16, 2007
    Assignee: Elite Products
    Inventor: Ronald Todd
  • Publication number: 20050140395
    Abstract: An overvoltage circuit detects differences between the supply voltage from a first circuit and the operating voltage of a second circuit. The circuit may detect when the power supply value of the first circuit is below, above, or equal to the operating voltage of the second circuit. The overvoltage circuit consumes substantially zero static current and may be used in a variety of implementations.
    Type: Application
    Filed: February 24, 2005
    Publication date: June 30, 2005
    Inventor: Ronald Todd
  • Patent number: 6883113
    Abstract: A procedure for temporally isolating an environmentally dependent integrated circuit fault includes the steps of determining a marginally failing and a minimally passing environmental condition corresponding to the fault; identifying a clock cycle Tmax at which the fault was first detected; determining a candidate clock cycle at which the fault may have occurred; and iteratively a) applying test pattern subsets from an initial clock cycle through the candidate clock cycle under the marginally failing environmental condition; b) applying remaining test patterns under the minimally passing environmental condition; and c) adjusting the candidate clock cycle based upon whether the fault occurred during test pattern subset application up through the candidate clock cycle under the marginally failing environmental condition. Candidate clock cycle adjustment in accordance with a binary search technique enables determination of an exact clock cycle at which the fault occurred in a maximum of Log2 (Tmax+1) iterations.
    Type: Grant
    Filed: April 18, 2002
    Date of Patent: April 19, 2005
    Assignee: Bae Systems Information and Electronic Systems Integration, Inc.
    Inventors: Bruce McWilliam, Ronald Todd, Thomas M. Storey
  • Publication number: 20030200484
    Abstract: A procedure for temporally isolating an environmentally dependent integrated circuit fault includes the steps of determining a marginally failing and a minimally passing environmental condition corresponding to the fault; identifying a clock cycle Tmax at which the fault was first detected; determining a candidate clock cycle at which the fault may have occurred; and iteratively a) applying test pattern subsets from an initial clock cycle through the candidate clock cycle under the marginally failing environmental condition; b) applying remaining test patterns under the minimally passing environmental condition; and c) adjusting the candidate clock cycle based upon whether the fault occurred during test pattern subset application up through the candidate clock cycle under the marginally failing environmental condition.
    Type: Application
    Filed: April 18, 2002
    Publication date: October 23, 2003
    Applicant: BAE Systems Information and Electronic Systems Integration, Inc.
    Inventors: Bruce McWilliam, Ronald Todd, Thomas M. Storey