Abstract: Disclosed is a process for forming self-aligned polysilicon gates and interconnecting conductors having a single conductivity and single impurity type in CMOS integrated circuits. After forming a polysilicon layer over the gate oxide, the polysilicon is doped with n-type impurities. Next, the polysilicon is covered with a relatively thick oxide serving as an implantation mask and then patterned into gates and conductors. Finally, by using ion implantation sources and drains for the p-FET and n-FET are formed in a self-aligned relationship with the corresponding gates.

Abstract: A coplanar CMOS process for fabricating self-aligned gate FETs utilizing high energy, high dose rate ion implants to form the S/D regions. In the course of coplanar processing, the gate electrodes and S/D regions are defined. Selectively prescribed thicknesses of silicon dioxide are then formed over the top and sidewalls of the gate electrodes, as well as the exposed substrate in the S/D regions. Thereafter, a first, silicon nitride layer of controlled thickness is evenly deposited, and is followed by a dry etch step to expose the thin layer of silicon dioxide covering the p-channel FET S/D regions. The temperature stability of silicon nitride protects the n-channel FETs from the effects of the high energy levels and currents associated with the ion implant step used to form the S/D regions of the p-channel FETs. In contrast, the implant ions readily penetrate the thin oxides over the S/D regions of the p-channel FETs. Thereafter, a second, silicon nitride layer of controlled thickness is deposited.

Abstract: Disclosed is a process for forming self-aligned all n.sup.+ -doped polysilicon gates and interconnections in CMOS integrated circuits. Polysilicon is formed into the n-FET gate, a barrier for the p-FET region and the interconnect pattern. Then, arsenosilicate glass (ASG) is formed over the interconnect and the p-FET gate and N-FET active regions. The p-FET gate is etched using the ASG as a mask. The device is heated driving in impurities from the ASG to n.sup.+ dope the polysilicon and form the n-FET source and drain. Then, boron is implanted in the p-FET source and drain regions.

Abstract: A process for forming a CIS (conductor-insulator-semiconductor) integrated circuit having one or more field-effect memory transistors, and one or more polysilicon resistors and/or polysilicon conductors. The polysilicon components are formed to predetermined sizes, as needed, so that the implant used to establish the memory threshold voltage of the transistor also provides the desired polysilicon resistance value(s). The process may be used to simultaneously form both memory and non-memory transistors.

Abstract: A process for forming a CIS (conductor-insulator-semiconductor) integrated circuit having one or more non-memory field-effect transistors, and one or more polysilicon resistors and/or polysilicon conductors. A single mask and implant sequence is used to establish the threshold voltage of the field-effect transistor and the resistance (conductance) of the polysilicon components. The polysilicon components are formed to predetermined sizes, as needed, so that the threshold-determining implant provides the desired polysilicon resistance value(s).

Abstract: An adhesion-enhancing technique for preparing the surface of a polycrystalline silicon body to receive organic photoresist. In an exemplary procedure, the polysilicon is placed in an oxygen plasma chamber operating under rf power of about 90 milliwatts per cubic centimeter of chamber volume and a pressure of approximately 1 torr for 10 minutes to form an adhesion-enhancing oxide monolayer on the polysilicon.