Abstract: A package for mounting I/C chips onto a circuit board is provided. The chip has a surface array of input/output pads on one side which forms a footprint. A carrier is formed of an organic dielectric material having opposite surfaces. A first set of bonding pads is formed on one surface of the chip carrier and arranged to correspond with the chip footprint. A first set of solder ball connections connects the input/output pads on the chip to the first set of bonding pads on the chip carrier. A second set of bonding pads is formed on the other surface of the chip carrier forming a second set of bonding pads. Electrically conducting vias extend through the chip carrier connecting the first set of bonding pads to the second set of bonding pads. An organic circuit board having a coefficient of thermal expansion similar to the chip carrier having electrical connector sites is provided, the sites are arranged in a pattern corresponding to the pattern of the second bonding pads on the chip carrier.

Abstract: A method and apparatus is provided for allowing computer functions formed on a flexible substrate to be adjacently stacked in layered relation. Each functional island will have an electrical connector on one end thereof. The electrical connector may include a plurality of conductive pads formed over solid vias that form a surface for electrically interconnecting adjacent flexible carriers of the functional islands. The solid vias and connection pads are also used to provide electrical communication between the reference plane, signal lines and chips that make up the functional islands, and chips contained on other functional islands, or on the planar. The plural functional islands are removably affixed to the planar by reflowing joining metallurgy on the connection pads of adjacent layers, or by using a compression type connector. The remaining portions of the functional islands are then flexibly placed within the computer system with varying amounts of space between the layers.

Abstract: A prepunched copper/dielectric laminate ground plane assembly is positioned on a metallized ceramic substrate having printed circuits on the surface thereof and provided with a plurality of circuit connection pins. Connection between the ground plane and the circuit connection pins is achieved by welding or soldering of bonding elements between selected pins, which also provides mechanical attachment of the ground plane to the substrate.