Abstract: A data bus system has a number of stations which are interconnected via a bus. The bus has a limited data transmission capacity available. From a transmitter station a resource control station reads which part of the available transmission capacity is required for the relevant transmitter. The resource control station allocates the required transmission capacity to the relevant transmitter station if adequate transmission capacity is available. Only if adequate transmission capacity is available is transmission by the relevant transmitter station enabled.

Abstract: A recording arrangement for recording trick mode information in portions of tracks includes at least two recording heads (A, B). Trick mode information recorded in the portions in the tracks enable a trick mode during reproduction in a reproducing arrangement having reading heads (50) for reading the trick mode information from the tracks, the reading heads including at least a first and a second reading head (A,B) located at the circumference of a head drum, and where the transport speed of the record carrier (40) in the said trick mode being n times the nominal transport velocity during normal play reproduction where n is an integer and comprises a divisor number p larger than 1. The trick mode information is recorded in such a way that in a group of 2p tracks (T.sub.2 to T.sub.7) the trick mode information is recorded in a portion of a first (T.sub.2), second (T.sub.3) and a third track (T.sub.5) in said group of 2p tracks, the first and second tracks (T.sub.2,T.sub.

Abstract: An apparatus of the helical scan type for reproducing a digital video signal from slant tracks (T) on a record carrier, the digital video signal having been recorded in first track portions (TP1) of the tracks. In an edit mode, the digital video signal is reproduced from the first track portions and a corresponding digital audio signal is recorded in second track portions (TP2) of the tracks. The apparatus includes at least one read head (RH) for reading the digital video signal recorded in the first track portions of the tracks and at least one write head (WH) for writing the second channel signal in the second track portions. The read head (RH) and the write head (WH) are positioned on a rotatable head drum at such a location relative to each other that when the read head reads the digital video signal from a first track portion of a first track (T.sub.i+24), the write head writes the second channel signal in a second track portion in a second track (T.sub.

Abstract: A method of transmitting timing critical data via an asynchronous channel without changing any datum to be transmitted. The timing critical data can be an MPEG transport stream. The asynchronous channel can be a computer or telephone network, a digital storage media such as a digital VCR, or a digital interface. The method involves tagging each transmission unit of the data stream, before inputting to the channel, with timing information, and using the timing information at the output end of the channel to recreate the proper data timing, Various schemes are described for packing the timing information tags with each or a plurality of transmission units.

Abstract: The invention proposes a testing method and associated arrangement for electronic circuitry that combines functional components that are interconnected by handshake channels. Various of such channels are now provided with an inbreaking junction and an outbreaking switch as a test component pair. The junction has two passive ports and one active port. The switch has one passive port and two active ports that are selected through a passive control port. In this way inbreaking into and outbreaking from the channel is rendered feasible. Now inbreaking is done on a first channel, and outbreaking on a second channel, so that thereby all components are tested that lie between the first channel's junction and the second channel's switch.

Abstract: During recording of an MPEG information signal on a record carrier (40), transport packets (P.sub.k) are stored in signal blocks in a track (1) on the record carrier (40). x transport packets of the MPEG information signal are stored in the second block sections (SB) of y signal blocks, where x and y are integers, x.gtoreq.1 and y>1, more specifically, y>x. Further, third block sections (TB) are present in one or more of the second block sections in the y signal blocks of a group for storing additional information, which additional information relates to the specific application of recording and reproducing the MPEG information signal on/from the record carrier.

Abstract: A write-acknowledge circuit includes a write detector and a bistable element. The write detector has two write inputs, two complementary inputs and an acknowledge output, and is constituted by only two transistors which are connected in series. The complementary inputs are the control inputs of the two transistors and the acknowledge output is output from their common connection point. The write inputs are respectively coupled to the two remaining terminals of the two transistors and also to the two respective inputs of the bistable element. The complementary inputs are coupled crosswise to the outputs of the bistable element. The write signals represent a 1-bit variable encoded according to the Double-Rail Encoding method. Four-phase handshake signalling is used for the write signals.

Abstract: A silicon-compilation method, a silicon-compiler arrangement, an abstract-circuit synthesis module usable in such arrangement, a machine-generated abstract circuit produced by such module, an electronic circuit generated by such method and a reset-free circuit produced by such arrangement. There are described a method and arrangement for silicon compilation. First, an algorithmic procedure to be executed by the electronic circuit is expressed in an imperative concurrent language. This, under execution of lexical, syntactic and semantic analysis is converted to a structure tree as an abstract representation of said procedure. This structure tree then is converted into an abstract circuit, wherein each basic component is a program module and each abstract channel corresponds to a program channel. Thereafter, the abstract circuit is converted into a concrete circuit, while obeying timing-organization constraints, circuitry-type constraints and technology constraints.