Abstract: Disclosed is a high speed sense amplifier circuit designed for sensing data in one-transistor DRAM memory cells on bit lines within DRAM macros. The circuit utilizes a charge transfer scheme to rapidly remove charge from a small sensing first capacitor C1, generating a voltage swing delta V1, via an FET operating in its subthreshold region by means of idling current, such transfer supplying an equal charge to the larger bit line capacitance Cb1 with small voltage swing delta Vb1. The sense amp is pre-charged to the “1” state, and senses a “0” via the charge transfer operation thusly described. A “1” is sensed when no charge transfer takes place.

Abstract: Disclosed is a high speed sense amplifier circuit designed for sensing data in one-transistor DRAM memory cells on bit lines within DRAM macros. The circuit utilizes a charge transfer scheme to rapidly remove charge from a small sensing first capacitor C1, generating a voltage swing delta V1, via an FET operating in its subthreshold region by means of idling current, such transfer supplying an equal charge to the larger bit line capacitance Cb1 with small voltage swing delta Vb1. The sense amp is pre-charged to the “1” state, and senses a “0” via the charge transfer operation thusly described. A “1” is sensed when no charge transfer takes place.

Abstract: A transistor with silicon on insulator (SOI) intrinsic base and a collector each formed by a low temperature epitaxial process and each orientated vertically with respect to the (SOI) substrate. The base width can be as narrow as in a conventional vertical transistor. Similarly, the collector width can be precisely controlled.

Abstract: A transistor with silicon on insulator (SOI) intrinsic base and a collector each formed by a low temperature epitaxial process and each orientated vertically with respect to the (SOI) substrate. The base width can be as narrow as in a conventional vertical transistor. Similarly, the collector width can be precisely controlled.

Abstract: A lateral bipolar transistor has an extrinsic base layer on either side of a centrally disposed emitter layer and an intrinsic base and a collector oriented perpendicularly to the extrinsic base and collector layers.

Abstract: A method of controlling the interfacial oxygen concentration of a monocrystalline/polycrystalline emitter includes the steps of: passivating the monocrystalline silicon surface by immersing the wafer in a diluted HF acid solution; transferring the wafer into a high vacuum environment; heating the wafer to between 400.degree. and 700.degree. C.; exposing the monocrystalline silicon surface to a gas having a partial pressure of oxygen of between 10.sup.-5 to 1 Torr for between 1 and 100 minutes; and, depositing polysilicon onto the monocrystalline silicon surface.

Abstract: A transistor memory cell is disclosed of the type wherein an unclamped conducting transistor in each of a plurality of memory cells connected to a given word line is driven into saturation when storing data. The cell is equipped with controlled active devices for discharging the saturation capacitance of the conducting transistors prior to writing new data into the cells. Each active device is characterized with a forward low-impedance current direction and reverse high impedance current direction therethrough for each saturation transistor. Each active device is connected to discharge an associated saturation transistor in its forward current direction. In one embodiment, each active device discharges to a word line when the line is brought to an appropriate control potential. In another embodiment, each active device discharges to a separate discharge line not connected to the work line when the former line is brought to an appropriate control potential. The active devices may be diodes.

Abstract: A read only memory utilizing a two-level cascoded current steering approach feeding a two-level common base isolation and sense amplifier network. The isolation network allows formation of a multi-way collector dot without deleterious effect upon the high speed current sensing operation. Single transistor cells with a common subcollector bed and common base rails as word lines make up the highly dense high speed array. The current source is provided by a current mirror circuit. The common-base, low impedance sense amplifier converts the sense current signal into a voltage swing which is then fed to the off-chip driver circuit via an emitter-follower pre-driver stage.

Abstract: A word redundancy scheme for a high speed RAM where the bit output stage uses on-chip logic. An extra emitter on each of the decoders is utilized including redundant word group decoders. A compare circuit has an output to each of the extra emitters and when the address of a bad bit arrives at the compare circuit it de-selects each of the non-redundant decoders at that address and selects the redundant decoders via the extra emitters. Hence, the redundant decoders replace the decoders of the bad bit position.

Abstract: Disclosed is a memory array in which each cell consists of a pair of cross coupled bipolar transistors with antisaturation clamps, a load resistor connected to the collector of each of the cross coupled transistors forming storage nodes, and Schottky barrier diode input/output devices connecting each node to a respective bit line. The emitters of the cross coupled transistors are connected to a lower word line while the load resistors are connected to an upper word line. Both the upper and lower word lines are switchable providing high speed as well as highly stable operation with very low power supply voltage requirements.

Abstract: A method for fabricating an N-channel silicon MOS field effect transistor on a P-type substrate. The structure retains the natural isolation between devices and the consequent higher device density in an integrated circuit structure than conventional double diffused MOS field effect transistor devices. The device is fabricated by using ion implantation to create an N-type surface layer in the channel and then overcompensating this layer to create a P-type region near the source by ion implanting P-type ions into the source junction region. The source to substrate capacitance is considerably less than that of conventional double diffused MOS devices which provides an improved circuit performance.

Abstract: A method for fabricating an N-channel silicon MOS field effect transistor on a P-type substrate. The structure retains the natural isolation between devices and the consequent higher device density in an integrated circuit structure than conventional double diffused MOS field effect transistor devices. The device is fabricated by using ion implantation to create an N-type surface layer in the channel and then overcompensating this layer to create a P-type region near the source by ion implanting P-type ions into the source junction region. The source to substrate capacitance is considerably less than that of conventional double diffused MOS devices which provides an improved circuit performance.

Abstract: A semiconductor device has a heavily doped semiconductor substrate with a lightly doped epitaxial layer overlying a surface of the substrate and of the same conductivity type as the substrate. Electrically insulating barriers extend from at least the surface of the epitaxial layer into the substrate so as to electrically isolate non-common areas of each surface leakage sensitive device within the epitaxial layer from the non-common areas of adjacent surface leakage sensitive devices.

Abstract: An over current protect circuit for a common bus driver having a complementary pair FET output includes a pair of AND circuits responsive to the gate-source and drain-source voltages for charging separate time integrating capacitors. If a threshold charge is reached a latch is triggered, which in turn disables the driver via a NAND gate and Inverter, and discharges the active capacitor. The latch is reset by dropping the driver enable line. As an alternative, high driver current may be sensed by placing a resistor in series with each output FET and charging the associated capacitor in response to a high current through the resistor.