Patents by Inventor Ronald W. Silvas
Ronald W. Silvas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230206383Abstract: A system includes a compression engine that stores the compression format information embedded in the compressed data. The compression format information can be included in a header that includes compression control surface (CCS) information. The system includes a shared memory to store compressed data for multiple hardware pipelines, where blocks of the compressed data have a common memory footprint and the compression header. The compression engine can compress data to store in the shared memory including generation of the header. The compression engine can decompress data read from the shared memory, including identification of the compression format from the header.Type: ApplicationFiled: December 23, 2021Publication date: June 29, 2023Inventors: Karol A. SZERSZEN, Prasoonkumar SURTI, Vidhya KRISHNAN, Aditya NAVALE, Abhishek R. APPU, Altug KOKER, Ronald W. SILVAS
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Publication number: 20230030741Abstract: Compressed verbatim copy can enable more efficient copying of compressed data. In one example, a compressed verbatim copy method involves receiving a command to copy compressed data from a source address of the memory device to a destination address. In response to the receipt of the command, the method involves copying the compressed data in a compressed format from the source address to the destination address without first decompressing the data. A second source address and a second destination address of metadata for the compressed data is determined, and the metadata is copied from the second source address to the second destination address.Type: ApplicationFiled: July 30, 2021Publication date: February 2, 2023Inventors: Nilay MISTRY, Karol A. SZERSZEN, Prasoonkumar SURTI, Ronald W. SILVAS
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Patent number: 11416402Abstract: Embodiments described herein provide an apparatus comprising a processor to allocate a first memory space for data for a graphics workload, the first memory comprising a first plurality of addressable memory locations, allocate a second memory space for compression metadata relating to the data for the graphics workload, the second memory space comprising a second plurality of addressable memory locations and having an amount of memory corresponding to a predetermined ratio of the amount of memory allocated to first memory space, and configure a direct memory mapping between the first plurality of addressable memory locations and the second plurality of addressable memory locations. Other embodiments may be described and claimed.Type: GrantFiled: October 12, 2020Date of Patent: August 16, 2022Assignee: INTEL CORPORATIONInventors: Niranjan L. Cooray, Altug Koker, Vidhya Krishnan, Ronald W. Silvas, John H. Feit, Prasoonkumar Surti, Joydeep Ray, Abhishek R. Appu
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Publication number: 20220197651Abstract: Examples described herein relate to a system that after decoding of video by the first device, provides a memory address of decoded video in the memory device to a second driver for a second device and perform a second device driver that causes the second device to access the decoded video directly from a translation of the memory address of the memory device, wherein the second device is to access the decoded video with memory properties of the decoded video and decompression information of the decoded video. In some examples, the first device comprises one or more of: a graphics processing unit integrated with a central processing unit (CPU), a discrete graphics processing unit, or a video decoder accelerator. In some examples, the second device comprises one or more of: a graphics processing unit integrated with a central processing unit (CPU) or a discrete graphics processing unit. In some examples, the memory properties of the decoded video comprise swizzle information.Type: ApplicationFiled: December 22, 2020Publication date: June 23, 2022Inventors: Gaurav KUMAR, Changliang L. WANG, Haichun DAI, Hongbin YE, Ronald W. SILVAS
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Publication number: 20210191878Abstract: An apparatus to facilitate page translations is disclosed. The apparatus comprises a frame buffer to a plurality of pages of data, a plurality of display page tables to store virtual address to physical address translations to the pages of data in the frame buffer and a page table having a plurality of page table entries (PTEs), wherein each PTE maps to one of the plurality of display page tables.Type: ApplicationFiled: December 23, 2019Publication date: June 24, 2021Applicant: Intel CorporationInventors: Ankur N. Shah, Geethacharan Rajagopalan, Ronald W. Silvas, Todd M. Witter
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Publication number: 20210049098Abstract: Embodiments described herein provide an apparatus comprising a processor to allocate a first memory space for data for a graphics workload, the first memory comprising a first plurality of addressable memory locations, allocate a second memory space for compression metadata relating to the data for the graphics workload, the second memory space comprising a second plurality of addressable memory locations and having an amount of memory corresponding to a predetermined ratio of the amount of memory allocated to first memory space, and configure a direct memory mapping between the first plurality of addressable memory locations and the second plurality of addressable memory locations. Other embodiments may be described and claimed.Type: ApplicationFiled: October 12, 2020Publication date: February 18, 2021Applicant: Intel CorporationInventors: NIRANJAN L. COORAY, Altug Koker, Vidhya Krishnan, Ronald W. Silvas, John H. Feit, Prasoonkumar Surti, Joydeep Ray, Abhishek R. Appu
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Patent number: 10802970Abstract: Embodiments described herein provide an apparatus comprising a processor to allocate a first memory space for data for a graphics workload, the first memory comprising a first plurality of addressable memory locations, allocate a second memory space for compression metadata relating to the data for the graphics workload, the second memory space comprising a second plurality of addressable memory locations and having an amount of memory corresponding to a predetermined ratio of the amount of memory allocated to first memory space, and configure a direct memory mapping between the first plurality of addressable memory locations and the second plurality of addressable memory locations. Other embodiments may be described and claimed.Type: GrantFiled: March 27, 2019Date of Patent: October 13, 2020Assignee: INTEL CORPORATIONInventors: Niranjan L. Cooray, Altug Koker, Vidhya Krishnan, Ronald W. Silvas, John H. Feit, Prasoonkumar Surti, Joydeep Ray, Abhishek R. Appu
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Publication number: 20200310973Abstract: Embodiments described herein provide an apparatus comprising a processor to allocate a first memory space for data for a graphics workload, the first memory comprising a first plurality of addressable memory locations, allocate a second memory space for compression metadata relating to the data for the graphics workload, the second memory space comprising a second plurality of addressable memory locations and having an amount of memory corresponding to a predetermined ratio of the amount of memory allocated to first memory space, and configure a direct memory mapping between the first plurality of addressable memory locations and the second plurality of addressable memory locations. Other embodiments may be described and claimed.Type: ApplicationFiled: March 27, 2019Publication date: October 1, 2020Applicant: Intel CorporationInventors: NIRANJAN L. COORAY, ALTUG KOKER, VIDHYA KRISHNAN, RONALD W. SILVAS, JOHN H. FEIT, PRASOONKUMAR SURTI, JOYDEEP RAY, ABHISHEK R. APPU
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Patent number: 9779472Abstract: A method and system for shared virtual memory between a central processing unit (CPU) and a graphics processing unit (GPU) of a computing device are disclosed herein. The method includes allocating a surface within a system memory. A CPU virtual address space may be created, and the surface may be mapped to the CPU virtual address space within a CPU page table. The method also includes creating a GPU virtual address space equivalent to the CPU virtual address space, mapping the surface to the GPU virtual address space within a GPU page table, and pinning the surface.Type: GrantFiled: May 13, 2016Date of Patent: October 3, 2017Assignee: Intel CorporationInventors: Jayanth N. Rao, Ronald W. Silvas, Ankur N. Shah
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Publication number: 20160328823Abstract: A method and system for shared virtual memory between a central processing unit (CPU) and a graphics processing unit (GPU) of a computing device are disclosed herein. The method includes allocating a surface within a system memory. A CPU virtual address space may be created, and the surface may be mapped to the CPU virtual address space within a CPU page table. The method also includes creating a GPU virtual address space equivalent to the CPU virtual address space, mapping the surface to the GPU virtual address space within a GPU page table, and pinning the surface.Type: ApplicationFiled: May 13, 2016Publication date: November 10, 2016Applicant: INTEL CORPORATIONInventors: Jayanth N. RAO, Ronald W. SILVAS, Ankur N. SHAH
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Patent number: 9378572Abstract: A method and system for shared virtual memory between a central processing unit (CPU) and a graphics processing unit (GPU) of a computing device are disclosed herein. The method includes allocating a surface within a system memory. A CPU virtual address space may be created, and the surface may be mapped to the CPU virtual address space within a CPU page table. The method also includes creating a GPU virtual address space equivalent to the CPU virtual address space, mapping the surface to the GPU virtual address space within a GPU page table, and pinning the surface.Type: GrantFiled: August 17, 2012Date of Patent: June 28, 2016Assignee: Intel CorporationInventors: Jayanth N. Rao, Ronald W. Silvas, Ankur N. Shah
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Publication number: 20140049551Abstract: A method and system for shared virtual memory between a central processing unit (CPU) and a graphics processing unit (GPU) of a computing device are disclosed herein. The method includes allocating a surface within a system memory. A CPU virtual address space may be created, and the surface may be mapped to the CPU virtual address space within a CPU page table. The method also includes creating a GPU virtual address space equivalent to the CPU virtual address space, mapping the surface to the GPU virtual address space within a GPU page table, and pinning the surface.Type: ApplicationFiled: August 17, 2012Publication date: February 20, 2014Applicant: INTEL CORPORATIONInventors: Jayanth N. Rao, Ronald W. Silvas, Ankur N. Shah