Abstract: Two integrated circuit die each having a processing core and on-board memory are interconnected and packaged together to form a multi-chip module. The first die is considered primary and the second die is considered secondary are connected through an interposer. The first and second die may be the same design and thus have the same resources such as peripherals and memory and preferably have a common system interconnect protocol. The core of the second die is disabled or at least placed in a reduced power mode. The first die includes minimal circuit for interconnecting to the second die. The second die has some required interface circuitry and an address translator. The result is that the core of the first die can perform transactions with the memory and other resources of the second integrated circuit as if the memory and other resources were on the first die.

Abstract: Two integrated circuit die each having a processing core and on-board memory are interconnected and packaged together to form a multi-chip module. The first die is considered primary and the second die is considered secondary are connected through an interposer. The first and second die may be the same design and thus have the same resources such as peripherals and memory and preferably have a common system interconnect protocol. The core of the second die is disabled or at least placed in a reduced power mode. The first die includes minimal circuit for interconnecting to the second die. The second die has some required interface circuitry and an address translator. The result is that the core of the first die can perform transactions with the memory and other resources of the second integrated circuit as if the memory and other resources were on the first die.

Abstract: A hard disk system for storing user data for an information device. The hard disk system includes a non-volatile, IC based memory such as e.g., a memory utilizing MRAM, to non volatilely store system data for the hard disk. Examples of system data include a master list, a list of unused sectors, and a list of defective sectors. In some examples, the master list includes the physical location on a hard disk where data of a file is stored. The non-volatile memory is operably coupled to a data storage system processor and may be implemented on a circuit board with the data storage system processor.

Abstract: A data storage system having a non IC based memory and an IC based non-volatile memory for storing user data. In one example, the IC based non-volatile memory is implemented with MRAM. Examples of non IC based memory include e.g. hard disks, tape, and compact disks. In some examples, the IC based memory is utilized to store user data from an information device in order to increase the speed and/or the effective storage capacity of the data storage system. In some examples, a portion of a standard size block of user data can be stored on spaces of the non IC based memory that are deficient for storing a standard size block with the remaining portion being stored in IC based memory. Portions of a file of user data may be non-volatilely stored in the IC based memory in order to more quickly provide the file to an information device. For example, data of a file, that if stored in a location on the non IC based media would significantly increase the retrieval time of the file, can be stored in the IC based media.

Abstract: A removable media data storage system with a memory for storing operational data regarding a removable media. In some examples, the operational data stored includes utilization data and/or system data. In some embodiments, the operational data is stored in a non-volatile IC based memory such as e.g. MRAM. In some examples, the memory can store multiple sets of operational data with one set for each removable media that has been inserted into the data storage system. The data system may include a processor operably coupled to the memory, wherein the memory and processor are located on a circuit board in the data system housing.

Abstract: A hardware system is provided for performing angle-to-time and time-to-angle conversions in a dynamic angular measurement and control system. The system has the capability of updating scheduled event times of other hardware timers in the system that are being used to generate output events at some specific angular position in the future. One application of the system is in automotive powertrain control systems in which the position of the engine is determined from a pulsed signal generated by a rotating crankshaft that accelerates and decelerates over time. The system performs critical calculations in hardware which consumes less CPU bandwidth than existing systems, resulting in potential cost savings for the overall system.

Abstract: A hard disk system for storing user data for an information device. The hard disk system includes a non-volatile, IC based memory such as e.g., a memory utilizing MRAM, to non volatilely store system data for the hard disk. Examples of system data include a master list, a list of unused sectors, and a list of defective sectors. In some examples, the master list includes the physical location on a hard disk where data of a file is stored. The non-volatile memory is operably coupled to a data storage system processor and may be implemented on a circuit board with the data storage system processor.

Abstract: A data storage system having a non IC based memory and an IC based non-volatile memory for storing user data. In one example, the IC based non-volatile memory is implemented with MRAM. Examples of non IC based memory include e.g. hard disks, tape, and compact disks. In some examples, the IC based memory is utilized to store user data from an information device in order to increase the speed and/or the effective storage capacity of the data storage system. In some examples, a portion of a standard size block of user data can be stored on spaces of the non IC based memory that are deficient for storing a standard size block with the remaining portion being stored in IC based memory. Portions of a file of user data may be non-volatilely stored in the IC based memory in order to more quickly provide the file to an information device. For example, data of a file, that if stored in a location on the non IC based media would significantly increase the retrieval time of the file, can be stored in the IC based media.

Abstract: A removable media data storage system with a memory for storing operational data regarding a removable media. In some examples, the operational data stored includes utilization data and/or system data. In some embodiments, the operational data is stored in a non-volatile IC based memory such as e.g. MRAM. In some examples, the memory can store multiple sets of operational data with one set for each removable media that has been inserted into the data storage system. The data system may include a processor operably coupled to the memory, wherein the memory and processor are located on a circuit board in the data system housing.

Abstract: A data storage system utilizing a non-volatile IC based storage media to reduce data retrieval time. The data storage system includes a non-volatile, non IC based storage system such as e.g. a hard disk. In one example, the non-volatile IC based storage media is implemented with MRAM. In one example, the processor of the storage system determines a seek time between sectors of the hard disk drive allocated to store a file of user data. Based upon the determined seek time, the processor non-volatilely stores a portion (e.g. the leading portion or the trailing portion) of a block of the user data in the MRAM. When the data is being accessed from the hard disk, the processor can provide the data stored in the MRAM while a read/write head moves between the sectors in order to decrease the access time for a file.

Abstract: A hardware system is provided for performing angle-to-time and time-to-angle conversions in a dynamic angular measurement and control system. The system has the capability of updating scheduled event times of other hardware timers in the system that are being used to generate output events at some specific angular position in the future. One application of the system is in automotive powertrain control systems in which the position of the engine is determined from a pulsed signal generated by a rotating crankshaft that accelerates and decelerates over time. The system performs critical calculations in hardware which consumes less CPU bandwidth than existing systems, resulting in potential cost savings for the overall system.

Abstract: A peripheral device selected with a chip select is mapped onto address space occupied by DRAM without causing internal or external contentions. A first address range is provided for accessing DRAM. A second address range is provided for accessing another device. The second address range is within the first address range. A row address strobe is provided for accesses within both the first and second address ranges but the column address strobe to the DRAM is inhibited when a memory access occurs within the second address range.

Abstract: Each of a plurality of output circuits is coupled with one pair of a plurality of pairs of adjacent odd and even bits of a sequential group of address bits. The output circuits provide an address bus with the odd address bits during a first time period and with the even address bits during a second time period. The odd address bits are provided as a column address (or a row address) and the even address bits are provided as the row address (or column address).

Abstract: A microcontroller is presented which is configurable to transfer data to and from one or more asynchronous serial ports (ASPs) using direct memory access (DMA), and having hardware features which cause each ASP to notify the microprocessor core (i.e., execution unit) when a data frame having a last data bit equal to a predetermined value is received. Such hardware features allow the execution unit to determine when complete data packets are received. Each ASP is adapted to receive serial communication data, and is configurable to generate an internal DMA request signal in response to the serial communication data. The serial communication data is transmitted within data frames, wherein each data frame includes multiple data bits transmitted sequentially between a start bit and one or more stop bits. The last data bit of the multiple data bits is transmitted immediately before the one or more stop bits.

Abstract: A DRAM controller is incorporated onto an existing microcontroller architecture. Existing chip select signals or other signals on the microcontroller are multiplexed with RAS and CAS signals. The RAS and CAS signals are asserted when an address is within a specific programmable address range and DRAM mode is enabled. The pins selected for RAS and CAS provide regular signals such as chip selects when not in DRAM mode. The timing of the chip select signal signals are adjusted when the chip select signals are utilized as column and row address strobes. Additionally, multiplexed addresses are provided from the microcontroller as well as refresh control. The microcontroller can provide high byte and low byte access by providing an upper column address strobe signal (UCAS) to support access for high byte and word access and a lower column address strobe signal (LCAS) to support low byte and word access. Mid range chip selects provide the UCAS and LCAS signals.

Abstract: A first plurality of address bits is provided to an address bus during a first time period. At least one banking address bit or at least one non banking address bit is selected according to a banking control signal, the selected bit being part a second plurality of address bits. The second plurality of address bits is multiplexed onto the address bus during a second time period. A first selector circuit receives a first and second group of address bits for a memory and outputs the first and second group during a first and second time period, respectively, according to a first select signal. A second selector circuit provides a subset of the second group to the first selector circuit, the second selector circuit selects a banking address group or a non banking address group as the subset according to a memory banking enable signal.

Abstract: A computer system is presented having a mechanism for re-mapping memory address space after system initiation. The mechanism includes a microcontroller embodying an integrated RAM controller and chip select unit. Select logic chooses between output from the chip select unit or output from the RAM controller, depending upon the state of memory chip select registers. The registers are set based upon whether a portion of the memory address space comprises ROM. If the space comprises ROM, then chip select signals are selected. After system initiation, data within ROM can be copied to a RAM, or loaded over a local or distal network, and the select logic chooses RAM controller output to operate the RAM.

Abstract: A method and apparatus for controlling a bus within a data processing system has a first control bit (SAS*), and second control bit (CLA*), and at least one termination signal (TA*, TRA*, TEA*). The CLA* signal is an input to a primary master (10). The primary master (10) provides a base address external to the primary master (10) so that a slave device can access the base address. The CLA* signal is asserted by the slave device to signal that the base address is to be cycled in a bit-wise circular fashion to provide a plurality of addresses out from the primary master (10) wherein each address in the plurality is derived from the base address internal to the primary master (10). Typically four addresses are provided per base address via the internal control of the primary master (10) in response to three sequential assertions of the CLA* signal.