Abstract: A double buffered flash bank. In one embodiment, a flash interface may be programmed by a register interface with a first set of data while a second set of data is being written to the register interface. In one embodiment, flash banks may be programmed in parallel using latched register interfaces. For example, while data from a first register interface is being written to the first flash bank and data from a second register interface is being written to a second flash bank, new data may be written to the first register interface and to the second register interface. The new data may then be written from the first register interface to the first flash bank and from the second register interface to the second flash bank.

Abstract: A method and apparatus for hot-docking is disclosed. In one embodiment, a portable computer system includes a bus bridge and a bus coupled to the bus bridge. The bus may have one or more peripheral devices or peripheral interfaces coupled to it. The bus may also be coupled to a docking interface having a bus switch. The bus switch, when closed and the computer is coupled to a docking station, may couple the bus to a peripheral interface in a docking station. The bus switch may close responsive to docking, thereby completing the electrical coupling of the bus to the peripheral interface in the docking station. The closing of the bus switch may be controlled by the docking interface such that operations on the bus are not interrupted during the docking procedure.

Abstract: A double buffered flash bank. In one embodiment, a flash interface may be programmed by a register interface with a first set of data while a second set of data is being written to the register interface. In one embodiment, flash banks may be programmed in parallel using latched register interfaces. For example, while data from a first register interface is being written to the first flash bank and data from a second register interface is being written to a second flash bank, new data may be written to the first register interface and to the second register interface. The new data may then be written from the first register interface to the first flash bank and from the second register interface to the second flash bank.

Abstract: A method and apparatus for hot-docking is disclosed. In one embodiment, a portable computer system includes a bus bridge and a bus coupled to the bus bridge. The bus may have one or more peripheral devices or peripheral interfaces coupled to it. The bus may also be coupled to a docking interface having a bus switch. The bus switch, when closed and the computer is coupled to a docking station, may couple the bus to a peripheral interface in a docking station. The bus switch may close responsive to docking, thereby completing the electrical coupling of the bus to the peripheral interface in the docking station. The closing of the bus switch may be controlled by the docking interface such that operations on the bus are not interrupted during the docking procedure.

Abstract: A static load for a high voltage driver includes first and second depletion mode field effect transistors and a diode-connected enhancement mode field effect transistor. The static load is arranged with a switching transistor to form a high voltage driver circuit. When the output of the driver circuit is at a relatively low potential, current drawn from the high voltage power supply is substantially reduced by applying a source to gate potential through the diode-connected transistor to one of the depletion mode transistors below the threshold voltage of the depletion mode transistor.

Abstract: Continuous power and a high rate clock are supplied to a calculator while it is in an execute mode and is actually decoding and processing input information, but lower duty cycle power and lower duty cycle clock pulses are supplied during the subsequent display mode, when the only requirement is to maintain and display selected information resulting from the execute cycle, so as to reduce the power consumption rate as compared to the rate during the execute mode. If there is no new execute mode within a selected time interval, the display is turned off and the duty cycle of the power and the clock supplied to the calculator are lowered still further so as to maintain (without displaying) selected stored information but to further reduce the rate of power consumption.