Abstract: A cochlear implant system can comprise an input source comprising a sensor and powered signal modifier. The sensor can be configured to receive a stimulus and output a signal representative of the received stimulus and the powered signal modifier can be configured to receive and modify the signal representative of the received stimulus to generate an input signal. The cochlear implant system can further comprise a signal processor in communication with the input source configured to output electrical power to the input source to power the powered signal modifier, receive the input signal from the input source, and generate a stimulation signal based on the received input signal. A cochlear implant system can also comprise an implantable battery and/or communication module, wherein the signal processor is configured to receive power signals from the implantable battery and/or communication module.

Abstract: A cochlear implant system can comprise an input source configured to receive a stimulus and generate an input signal representative of the stimulus, a cochlear electrode, a stimulator in communication with the cochlear electrode configured to provide electrical stimulation to cochlear tissue via the cochlear electrode, and a signal processor programmed with a first pulse rate. The signal processor can be configured to receive the input signal from the input source and filter the input signal based on the first pulse rate such that one or more frequencies associated with the first pulse rate in the received input signal are attenuated. The signal processor can further be configured to output a stimulation signal to the stimulator based on the filtered input signal with the stimulation signal causing the stimulator to provide electrical stimulation to the cochlear tissue at the first pulse rate.

Abstract: A processor and processing method for reusing arbitrary sections of program code provides improved upgrade capability for systems with non-alterable read only memory (ROM) and a more flexible instruction set in general. A specific program instruction is provided in the processor instruction set for directing program execution to a particular start address, where the start address is specified in conjunction with the specific program instruction. An end address is also specified in conjunction with the specific program instruction and the processor re-directs control upon completion of code execution between the start and end address to either another specified address, or to a stored program counter value corresponding to the next instruction in sequence after the specific program instruction. A loop count may also be supplied for repeatedly executing the code between the start and end address until the count has expired.