Abstract: Disclosed is a field effect transistor (FET) circuit utilizing three sources of potential, the third source of potential being derived from the substrate. An input stage, connected between first and second sources of potential, is adapted to receive a logic input signal approximating said first and second sources of potential. An output stage connected between the first source of potential and a third source of potential, is adapted to provide a logical output signal approximating said first and third sources of potential. The third source of potential, which is derived from the substrate, provides a potential level suitable for turning off depletion mode FET devices.

Abstract: Disclosed is a field effect transistor (FET) driver circuit capable of full supply voltage signal swings and high switching speeds while dissipating relatively little power. The output is obtained from a node between two series connected enhancement mode devices. The first of these series connected enhancement mode devices receives an input signal at its gating electrode, while the second of this pair of series connected devices has its gating electrode capacitively coupled to the output node through a first gatable depletion mode device. The first depletion mode device is in a series electrical path with a second depletion mode device and an enhancement mode device. The second depletion mode device and the enhancement mode device in series therewith receive the same phase of the input signal as the gate of said one series connected output transistor while the first gated depletion mode device is either self-biased or gets a gating input that is out of phase therewith.