Abstract: A voltage comparator with hysteresis that includes a differential amplifier, voltage divider circuits and a current mirror circuit. The input terminals of the two differential amplifier circuit branches are biased at unequal potentials by the voltage divider circuits. One voltage divider output voltage is fixed and the other is variable. The input terminal of the differential amplifier circuit branch biased at the fixed potential receives an AC-coupled input signal voltage. The sum of the input signal voltage and the fixed bias voltage is compared against the variable bias voltage. A current mirror circuit, which is activated during conduction by the differential amplifier circuit branch biased at the variable potential, shunts a portion of the current used by the voltage divider circuit that generates the variable potential. This causes the variable voltage divider output voltage to change, thereby introducing hysteresis into the voltage comparison performed by the differential amplifier.

Abstract: An input signal voltage clamping circuit that provides asymmetrical, or unipolar, voltage clamping for an input signal terminal of a circuit. For a circuit having a positive power supply voltage relative to its ground, or reference, terminal and an input signal having positive and negative signal peaks, the input signal terminal voltage is clamped at positive and zero voltage levels. The input signal terminal voltage is clamped at a positive clamp voltage level which is intermediate to the power supply and ground potentials when the input signal voltage is greater than such positive clamp voltage. The input signal terminal voltage is clamped at a zero volt level when the input signal voltage is negative.