Abstract: An improved clock distribution system is provided for a multi block network having a series of independent blocks, with each independent block having an average load tap signal. The clock distribution circuit uses the load tap signal from the slowest independent block to synchronize the clock used in the remaining blocks. The clock for the subsequent block is tuned to the average load tap signal of the slowest block. The system clock system is incrementally delayed until it is in tuned with the average load tap signal of the slowest block, then if can be provided to the subsequent blocks of the network. The clock distribution system comprises sequential delay stages to incrementally delay the reference clock signal. The shift register controls each stage of delay, by enabling a multiplexer to allow the incrementally delayed reference clock signal to pass through.