Abstract: A data processing device is described with a memory and a first and a second data processing component. The first data processing component comprises a control memory comprising, for each memory region of a plurality of memory regions of the memory, an indication whether a data access to the memory region may be carried out by the first data processing component and a data access circuit configured to carry out a data access to a memory region of the plurality of memory regions if a data access to the memory region may be carried out by the first data processing component; and a setting circuit configured to set the indication for a memory region to indicate that a data access to the memory region may not be carried out by the first data processing component in response to the completion of a data access of the first data processing component to the memory region.

Abstract: For reconstructing a data clock from asynchronously transmitted data packets, a control loop is provided which includes a controlled oscillator. An input signal of the control loop is generated on the basis of the received data packets. At least one high-pass type filter is provided in a signal path of the control loop. The data clock for the synchronous output of data is generated on the basis of an output signal of the controlled oscillator.

Abstract: A method and a system for providing information for recovering a clock frequency via a data network comprise generating a value representative of a frequency difference between a clock frequency and a reference frequency by using a digital phase-locked loop at an ingress interface of a data network, transmitting the generated value over the data network, and recovering the clock frequency at an egress interface of the data network by using the reference frequency and the transmitted value. Other systems and methods are also disclosed.

Abstract: A data processing device is described with a memory and a first and a second data processing component. The first data processing component comprises a control memory comprising, for each memory region of a plurality of memory regions of the memory, an indication whether a data access to the memory region may be carried out by the first data processing component and a data access circuit configured to carry out a data access to a memory region of the plurality of memory regions if a data access to the memory region may be carried out by the first data processing component; and a setting circuit configured to set the indication for a memory region to indicate that a data access to the memory region may not be carried out by the first data processing component in response to the completion of a data access of the first data processing component to the memory region.

Abstract: At an ingress interface of a data network first information data are generated, at an egress interface of the data network second information data are generated, correction data are generated on the basis of the second information data, and at the egress interface a clock frequency is recovered on the basis of the first information data and the correction data.

Abstract: For reconstructing a data clock from asynchronously transmitted data packets, a control loop is provided which includes a controlled oscillator. An input signal of the control loop is generated on the basis of the received data packets. At least one high-pass type filter is provided in a signal path of the control loop. The data clock for the synchronous output of data is generated on the basis of an output signal of the controlled oscillator.

Abstract: A method and device for controlling the phase of successively transmitted frames, in which data symbols are transmitted at a constant symbol frequency, in which a phase difference between the clock of the frame transmission and a data clock is determined and, dependent on the phase difference, an adjusting signal is produced for controlling the injection of stuffing data symbols into the frames for changing the frame length and the phase of the frame transmission, whereby the phase of the frame transmission is controlled so that the frames are transmitted on average synchronously with the data clock, wherein the adjusting signal is produced dependent on the phase difference determine from N frame in each successively transmitted, whereby N is at least 2.

Abstract: At an ingress interface of a data network first information data are generated, at an egress interface of the data network second information data are generated, correction data are generated on the basis of the second information data, and at the egress interface a clock frequency is recovered on the basis of the first information data and the correction data.

Abstract: A method and a system for providing information for recovering a clock frequency via a data network comprise generating a value representative of a frequency difference between a clock frequency and a reference frequency by using a digital phase-locked loop at an ingress interface of a data network, transmitting the generated value over the data network, and recovering the clock frequency at an egress interface of the data network by using the reference frequency and the transmitted value. Other systems and methods are also disclosed.

Abstract: The invention relates to a method for detection of impedances, in particular along inductances, in telephone lines of the type with two metal wires as signal conductors (twisted pair), having the following method steps: a test signal in the form of an AC voltage is fed into the telephone line, a measurement signal of the reflection signal of the test signal is measured, which can be tapped off the input impedance of the entire line at the start of the line, the first method steps are carried out at a number of different frequencies within a preselected frequency range of the AC voltage of the test signal, the profile of the measurement signals is analyzed as a function of the frequency, with the derivative of the profile of the measurement signals being formed based on the frequency, at which point the second derivative of the profile of the measurement signals is formed based on the frequency, the profile of the second derivative of the profile of the measurement signals based on the frequency is investigat

Abstract: The invention relates to a method for detection of impedances, in particular along inductances, in telephone lines of the type with two metal wires as signal conductors (twisted pair), having the following method steps: a test signal in the form of an AC voltage is fed into the telephone line, a measurement signal of the reflection signal of the test signal is measured, which can be tapped off the input impedance of the entire line at the start of the line, the first method steps are carried out at a number of different frequencies within a preselected frequency range of the AC voltage of the test signal, the profile of the measurement signals is analyzed as a function of the frequency, with the derivative of the profile of the measurement signals being formed based on the frequency, at which point the second derivative of the profile of the measurement signals is formed based on the frequency, the profile of the second derivative of the profile of the measurement signals based on the frequency is investigate

Abstract: The invention relates to a method for production of a transmission signal with reduced crest factor having the following method steps: (a) Provision of a transmission signal which is to be transmitted and has at least one peak value in one area; (b) sampling, in particular oversampling of the transmission signal in order to produce sample values; (c) buffer-storage and/or delay of the transmission signal s1(+) corresponding to the delay in the production of a correction function; (d) production of a weighted correction function by detection of whether the magnitude of the transmission signal or of its sample values has exceeded a first threshold in this area of the transmission signal; calculation of a correction factor; production of a weighted correction function from the correction factor and from a predetermined correction function; (e) additives superimposition of the weighted correction function and the delayed and/or buffer-stored transmission signal in order to produce the transmission signal with a

Abstract: A method and a device are presented for generating a system clock (OC) of a transmitting and/or receiving device with the aid of a system oscillator (1, 2). At least one control signal (PS, FS, JS, IS) is thereby evaluated by an evaluation unit (12) and the system oscillator (1, 11) is actuated as a function of this control signal (PS, FS, JS, IS) in order to change its frequency. This makes it possible for problems which arise due to an excessive frequency tolerance of an oscillating quartz element (1) to be eliminated or avoided by preventive means.

Abstract: With plesiochronous data communication, as in particular S(H)DSL transmission, data symbols (2) are transmitted at a constant symbol frequency in frames (1) with a time duration variable within limits. The length of the frames (1) is varied by inserting or omitting stuffing data symbols in relation to a nominal length, so that it is averaged over several frames (1) synchronously with a data clock. If the data clock frequency is synchronous with the symbol frequency, alternating stuffing data symbols are injected or omitted in the frames (1), so that the phase of the frames (1) varies constantly during the transmission. This variation however occurs at a high frequency and can be easily suppressed on the receiving side when recovering the data clock by means of a PLL.

Abstract: A clock signal generator for generating a clock signal with minimum phase jitter at a clock signal generator output (41), the clock signal generator (1) having: a DT oscillator (4) which is clocked with an input clock signal and generates a periodic digital DTO output signal, a phase displacement calculation unit (12) for calculating the phase displacement between the signal phase of the DTO output signal and the signal phase of the most significant bit MSB of the DTO output signal, and a phase displacement reduction unit for reducing the phase displacement between the signal phase of the DTO output signal and the signal phase of the most significant bit MSB of the DTO output signal as a function of the calculated phase displacement, the most significant bit MSB being output with reduced phase displacement as a clock signal to the clock signal generator output (41).

Abstract: In order to generate a pulsed signal with a desired active state without a great outlay on circuitry, the circuit according to the invention is characterized by a first and a second transistor (2, 3) in the integrated circuit, which are connected in series between a supply potential (UDD) and ground (GND), firstly a control pulse (A) having the predetermined duration being present at a control connection (G1) of the first transistor (2) and then a control pulse (B) being present at a control connection (G2) of the second transistor (3), with the result that, for the predetermined duration, firstly the first transistor (2) and then the second transistor (3) is turned on, and a resistor (6, 7) for the definition of the active signal state, which is connected outside the integrated circuit in parallel with one of the two transistors (2, 3) in the integrated circuit either between the supply potential (UDD) and the connecting point (4) or between ground (GND) and the connecting point (4).

Abstract: A clock signal generator for generating a clock signal with minimum phase jitter at a clock signal generator output (41), the clock signal generator (1) having: a DT oscillator (4) which is clocked with an input clock signal and generates a periodic digital DTO output signal, a phase displacement calculation unit (12) for calculating the phase displacement between the signal phase of the DTO output signal and the signal phase of the most significant bit MSB of the DTO output signal, and a phase displacement reduction unit for reducing the phase displacement between the signal phase of the DTO output signal and the signal phase of the most significant bit MSB of the DTO output signal as a function of the calculated phase displacement, the most significant bit MSB being output with reduced phase displacement as a clock signal to the clock signal generator output (41).

Abstract: The present invention is related to a device for the radio transmission of telephone calls via several base stations which are spatially separated from mobile phones being in a DECT standard. The spatially separated base stations can be connected to the telephone network via several switching centers which are also spatially separated, whereby an additional line is then connected between the switching centers for measuring the running time between the switching centers and for synchronization.

Abstract: A circuit configuration for measuring a phase difference between a reference signal and a clock signal includes a first shift register being clocked by the clock signal and having an input receiving the reference signal. A digital differentiator is connected downstream of the first shift register and has an output. A counter has an input receiving the clock signal and an output outputting a multidigit binary word. A buffer memory is connected to the counter and to the digital differentiator for storing the binary word at the output of the counter in memory upon an appearance of a corresponding output signal of the digital differentiator. The buffer memory has an output forming most significant bits of an output binary word. A second shift register is inversely clocked by the clock signal and has an input receiving the reference signal and an output. An analog differentiator has an input connected to the output of the digital differentiator and an output.

Abstract: A signal transmission apparatus includes a higher-level station, a lower-level station and a digital transmission device connected between the stations and having a signal transit time to be measured. Each of the stations has a transmitter for sending useful signals, each clocked by a respective clock signal, through the transmission device to other station. Each of the stations has a receiver for receiving the useful signals clocked by the other station and for separating out the clock signal superimposed on the applicable useful signal. The useful signal to be transmitted in the higher-level station is clocked by a given clock signal. The useful signal to be transmitted in the lower-level station is clocked by a clock signal derived from the clock signal separated out from the receiver of the lower-level station.