Patents by Inventor Ronalu Augusta Nunes Barcelos

Ronalu Augusta Nunes Barcelos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10936776
    Abstract: Various embodiments provide for analyzing (e.g., debugging) waveform data generated for a simulated circuit design, which can be used as part of electronic design automation (EDA). For example, where a user modifies a circuit design in a manner that impacts a next simulation run performed on the circuit design, various embodiments perform the next simulation run only on one or more portions of the circuit design affected by the user's modifications, while the results/simulated values for the rest of the circuit design are kept or reused.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: March 2, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Chien-Liang Lin, Thamara Karen Cunha Andrade, Ronalu Augusta Nunes Barcelos, Gabriel Peres Nobre, Igor Tiradentes Murta, Vitor Machado Guilherme Barros, Rafael Sales Medina Ferreira, Marcos Augusto de Goes
  • Patent number: 10540467
    Abstract: The present disclosure relates to a method for electronic circuit design. Embodiments may include receiving, using a processor, an electronic circuit design and identifying at least one combinational loop associated with the electronic circuit design. Embodiments may also include extracting, for each component of the loop, a set of logic conditions and modeling the at least one combinational loop. Embodiments may further include providing a graphical user interface configured to display one or more constraint candidates and determining whether or not a conflict exists between constraint candidates. Embodiments may also include ranking the constraint candidates, based upon, at least in part, a number of loops disabled and one or more disabled loop characteristics.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: January 21, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Craig Franklin Deaton, Abner Luis Panho Marciano, Matheus Nogueira Fonseca, Ronalu Augusta Nunes Barcelos, Fabiano Cruz Peixoto
  • Patent number: 10289798
    Abstract: The present disclosure relates to a method for debugging associated with formal verification of an electronic design. Embodiments may include performing, using a processor, an initial formal verification of an electronic design. Embodiments may further include identifying one or more counter-examples associated with one or more assertion properties of the electronic design or identifying one or more cover-traces associated with one or more cover properties of the electronic design. Embodiments may further include generating a trace core for each of the one or more counter-examples or cover-traces, wherein each trace core includes a minimal representation of the counter-example or cover-trace. Embodiments may further include identifying a similarity between a plurality of the trace cores and clustering the plurality of trace cores having the similarity.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: May 14, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Ronalu Augusta Nunes Barcelos, Hudson Dyele Pinheiro de Oliveira, Mirlaine Aparecida Crepalde, Lucas Luz Reckziegel, Glauber Tadeu de Sousa Carmo, Augusto Amaral Mafra, Regina Mara Amaral Fonseca, Guilherme Henrique de Sousa Santos, Valdir Antoniazzi JĂșnior