Abstract: An event aggregation fabric, implemented over an Integrated Circuit (IC) may include a Directed Acyclic Graph (DAG), including one or more aggregation nodes. Each aggregation node may receive input cue signals, originating from one or more source modules in the IC via respective one or more lean (e.g., single-wire) connections, indicate occurrence of events in respective source modules. The aggregation node may maintain a deficit count of the input cue signals, and generate an output cue signal, based on the deficit count. When the aggregation node is a terminal node of the DAG, it may transfer the output cue signal as an aggregated indication, representing occurrence of events in the source modules, to a target module in the IC. Otherwise, the aggregation node may transfer the output cue signal via lean connection to a subsequent aggregation node of the DAG, towards the terminal node.

Abstract: An Integrated Circuit (IC) device, and a method of utilizing thereof, may include: a plurality of Processing Elements (PEs), each comprising one or more configurable hardware logic blocks. The IC may further include a plurality of configuration memory elements, each associated with a respective PE, and adapted to maintain two or more configuration settings of the respective PE. The IC may further include a configuration manager circuit, configured to: receive a reconfiguration instruction, dictating a required function of the IC device; based on the reconfiguration instruction, identify at least one target PE of the plurality of PEs as a target for reconfiguration; based on the required function, select a specific configuration setting in the configuration memory element associated with the at least one target PE; and reconfigure at least one hardware logic block of the at least one target PE, according to the selected configuration setting.

Abstract: A system for accessing memory, comprising: transformation circuitry configured to: receive a memory access request; access a transformation mode value associated with the memory access request and indicative of an address transformation function; apply the address transformation function, indicated by the transformation mode value, to a memory address of the memory access request to compute a transformed memory address; and generate a new memory access request using the memory access request and the transformed memory address; and at least one memory area configured to serve the new memory access request according to the transformed memory address.

Abstract: A system for executing multiple concurrent threads, comprising: context storages, each configured to store thread contexts, each context for one of the multiple threads, each of the context storages associated with an operation of the threads; and processing circuitry configured to: while a first and a second thread are executed simultaneously by the circuitry: store a first context of the first thread in a first storage, identified in the first storage by a value; store a second context of the second thread in a second storage, identified in the second storage by the value; and upon completing execution of a first operation of the first thread, the operation associated with the first storage, when applying a test to the value indicates that the value is available in the second storage, store the first context in the second storage, the first context identified in the second storage by the value.

Abstract: A system for processing a plurality of concurrent threads comprising: a reconfigurable processing grid, comprising logical elements and a context storage for storing thread contexts, each thread context for one of a plurality of concurrent threads, each implementing a dataflow graph comprising an identified operation; and a hardware processor configured for configuring the at reconfigurable processing grid for: executing a first thread of the plurality of concurrent threads; and while executing the first thread: storing a runtime context value of the first thread in the context storage; while waiting for completion of the identified operation by identified logical elements, executing the identified operation of a second thread by the identified logical element; and when execution of the identified operation of the first thread completes: retrieving the runtime context value of the first thread from the context storage; and executing another operation of the first thread.

Abstract: An Integrated Circuit (IC) device, and a method of utilizing thereof, may include: a plurality of Processing Elements (PEs), each comprising one or more configurable hardware logic blocks. The IC may further include a plurality of configuration memory elements, each associated with a respective PE, and adapted to maintain two or more configuration settings of the respective PE. The IC may further include a configuration manager circuit, configured to: receive a reconfiguration instruction, dictating a required function of the IC device; based on the reconfiguration instruction, identify at least one target PE of the plurality of PEs as a target for reconfiguration; based on the required function, select a specific configuration setting in the configuration memory element associated with the at least one target PE; and reconfigure at least one hardware logic block of the at least one target PE, according to the selected configuration setting.

Abstract: A data analytics system/method operative in conjunction with a data repository storing data regarding each of a multiplicity of frames including images of ID documents, including receiving at least one image generated by an image capturing device such as a camera or scanner; providing document data, derived by a hardware processor from the image capturing device, which characterizes a document depicted in the image; providing person data, derived by a hardware processor from the image, which characterizes a person who may bear the document depicted in the image; and generating inputs for identification of potential fraudulent attempts including analyzing whether the document data exists within the data regarding each of the multiplicity of images of ID documents; and/or analyzing whether the person data exists within the data regarding each of the multiplicity of images of ID documents.

Abstract: A data analytics system/method operative in conjunction with a data repository storing data regarding each of a multiplicity of frames including images of ID documents, including receiving at least one image generated by an image capturing device such as a camera or scanner; providing document data, derived by a hardware processor from the image capturing device, which characterizes a document depicted in the image; providing person data, derived by a hardware processor from the image, which characterizes a person who may bear the document depicted in the image; and generating inputs for identification of potential fraudulent attempts including analyzing whether the document data exists within the data regarding each of the multiplicity of images of ID documents; and/or analyzing whether the person data exists within the data regarding each of the multiplicity of images of ID documents.

Abstract: A computing method includes accepting a definition of a computing task, which includes multiple Processing Elements (PEs) having execution dependencies. The computing task is compiled for concurrent execution on a multiprocessor device, by arranging the PEs in a series of two or more invocations of the multiprocessor device, including assigning the PEs to the invocations depending on the execution dependencies. The multiprocessor device is invoked to run software code that executes the series of the invocations, so as to produce a result of the computing task.

Abstract: A computing method includes accepting a definition of a computing task, which includes multiple Processing Elements (PEs) having execution dependencies. The computing task is compiled for concurrent execution on a multiprocessor device, by arranging the PEs in a series of two or more invocations of the multiprocessor device, including assigning the PEs to the invocations depending on the execution dependencies. The multiprocessor device is invoked to run software code that executes the series of the invocations, so as to produce a result of the computing task.

Abstract: A computing method includes accepting a definition of a computing task, which includes multiple Processing Elements (PEs) having execution dependencies. The computing task is compiled for concurrent execution on a multiprocessor device, by arranging the PEs in a series of two or more invocations of the multiprocessor device, including assigning the PEs to the invocations depending on the execution dependencies. The multiprocessor device is invoked to run software code that executes the series of the invocations, so as to produce a result of the computing task.

Abstract: A computing method includes accepting a definition of a computing task, which includes multiple Processing Elements (PEs) having execution dependencies. The computing task is compiled for concurrent execution on a multiprocessor device, by arranging the PEs in a series of two or more invocations of the multiprocessor device, including assigning the PEs to the invocations depending on the execution dependencies. The multiprocessor device is invoked to run software code that executes the series of the invocations, so as to produce a result of the computing task.