Abstract: Methods and systems for processing data are disclosed. An exemplary system for parsing and modifying data stored in an array of storage elements includes a parsing system configured to access the data stored in selected storage elements of the array of storage elements and output the data in one of a plurality of register formats and a write system configured to write data to selected storage elements of the array of storage elements, wherein the data is received in one of the plurality of register formats. The plurality of register formats includes a first set of register formats corresponding to a packed representation of the data and a second set of register formats corresponding to an unpacked representation of the data.

Abstract: In general, a system and method for implementing DSL support for use by a computer having a PCI bus is disclosed. A DSL modem is allowed to simultaneously communicate data to and from the computer. In a simplified embodiment, a DSL enabling device provides both data flow control and general control functions of the DSL modem. The DSL enabling device comprises a PCI DMA arbitrator, which determines the status of a temporary memory module in response to either a transmit request from a transmit control unit or a receive request from a receive control unit, thereby arbitrating between the two control units in order to access the temporary memory module. A read/write register specifies priority between the transmit control unit and the receive control unit, as well as specifying computer memory addresses to write to and setting memory cell length.

Abstract: In general, a system and method for providing PCI power management support without requiring a clock is disclosed. A computer is allowed to reside in a sleep mode and receive a power management event signal from an attached peripheral device in response to an external action request from an external source, thereby waking the computer and initializing device drivers to allow the peripheral device to perform predefined functions. During initiation of the power management system, the system provides a peripheral device with a PME_Status bit. In response to an external event, the peripheral device receives an external action request from the source of the external event. The peripheral device then sets the PME_Status bit and transmits a power management event (PME) signal to a computer operating system. Upon receiving the PME signal, the computer turns back on. The computer operating system then searches all peripheral devices connected to the computer for the set PME_Status bit.

Abstract: The present invention is directed to an improved direct memory access (DMA) controller for executing commands having an extremely compact structure, and which may be stored in an external memory. In accordance with one aspect of the present invention, a DMA controller is provided having circuitry configured to receive a memory segment, wherein the memory segment comprises a plurality of contiguous bytes from an external memory. The DMA controller also includes circuitry configured to parse the received memory segment into a plurality of distinct segments. The controller also includes circuitry configured to store the plurality of distinct segments into a plurality of internal registers, wherein the plurality of internal registers includes a command register. Finally, the DMA controller includes circuitry configured to decide the value stored in the command register to identify an instruction for execution.

Abstract: The present invention is directed to an improved direct memory access (DMA) controller for executing commands having an improved instruction set. In accordance with one aspect of the present invention, a DMA controller is provided having an enhance command set. Specifically, a DMA controller is provided having the ability to perform a memory fill command. Thus, in accordance with one aspect of the invention, a method is provided for controlling a DMA controller to execute a memory fill command, wherein the method obtains a starting address, a segment length identifier, and a data value. Preferably, this information is obtained by reading successive bytes from external memory. The method then writes the data value to a plurality of consecutive locations in the memory, beginning at the starting address, wherein the number of consecutive locations written to is equal to the segment length identifier.

Abstract: The present invention is directed to an improved direct memory access controller, having built-in arbitration circuitry, whereby multiple, identical, DMA controllers may be cascaded within a computing system, without requiring additional (i.e., separate) arbitration circuitry. In accordance with one aspect of this invention, a DMA controller is provided having a first input for connection to a DMA Acknowledge signal, and a first output for connection to a DMA Request. A second output is also provided for carrying a signal that is representative of activity of the DMA controller. In this regard, the second output may be configured to output a signal in either an Enable state or Inhibit state. If the DMA controller is active (i.e., presently controlling the transfer update among memory devices), then the second output is placed in an Inhibit state. Otherwise, the second output is controlled to be in an Enabled state.

Abstract: In general, the system and method provides a balanced clock distribution between two devices. A first output buffer, located in a source chip, provides buffering of a clock signal, after which, the delayed clock signal is transmitted to a destination chip, as well as to a balancing buffer located in the source chip. In addition, a second buffer, also located in the source chip, provides buffering of a data signal, after which, the data signal is transmitted to the destination chip. Both the clock and the data signals are then further buffered by first and second input buffers respectfully, which are located on the destination chip. After the delayed clock signal has been received by the balancing buffer, the balancing buffer provides a balancing delay to the delayed clock signal in accordance with the delay provided by the first input buffer, located in the destination chip, so as to provide a balanced clock distribution between the source chip and the destination chip.