Abstract: A novel and useful apparatus for and method of distributed coexistence for mitigating interference in a single chip radio and/or a multi-radio (i.e. multi-transceiver) communications device. The invention enables coexistence ‘friendly’ radio IPs having frequency agility in that they are capable of shifting their clock frequencies thereby avoiding frequency bands of potential victim radios. Frequency agility on the aggressor radio side (rather than by mitigating the effect of interference on the victim radio side) prevents harmonics from the aggressor's clock scheme from falling in the operating frequency band of the victim radio, and in turn causing degradation to its performance. Each aggressor radio, based on information received from other radios, configures the root clock frequency of its RX and/or TX chain clock generation circuits.

Abstract: A system for terminating a receive correlation window of a receiving wireless device includes a radio frequency receiver configured to open a receive correlation window having a predetermined duration and an energy measurement circuit configured to measure a radio frequency energy level ambient to the wireless receiver. A comparator is included that is configured to determine, based on the measured radio frequency energy level, whether or not a signal is being transmitted from a nearby wireless device. The receiver is further configured to close the receive correlation window before the predetermined duration is reached in response to a determination by the comparator that no signal is being transmitted by a nearby device. If a signal is being transmitted, then the receive correlation window is allowed to proceed uninterrupted.

Abstract: A system for terminating a receive correlation window of a receiving wireless device includes a radio frequency receiver configured to open a receive correlation window having a predetermined duration and an energy measurement circuit configured to measure a radio frequency energy level ambient to the wireless receiver. A comparator is included that is configured to determine, based on the measured radio frequency energy level, whether or not a signal is being transmitted from a nearby wireless device. The receiver is further configured to close the receive correlation window before the predetermined duration is reached in response to a determination by the comparator that no signal is being transmitted by a nearby device. If a signal is being transmitted, then the receive correlation window is allowed to proceed uninterrupted.

Abstract: A novel and useful apparatus for and method of distributed coexistence for mitigating interference in a single chip radio and/or a multi-radio (i.e. multi-transceiver) communications device. The invention enables coexistence ‘friendly’ radio IPs having frequency agility in that they are capable of shifting their clock frequencies thereby avoiding frequency bands of potential victim radios. Frequency agility on the aggressor radio side (rather than by mitigating the effect of interference on the victim radio side) prevents harmonics from the aggressor's clock scheme from falling in the operating frequency band of the victim radio, and in turn causing degradation to its performance. Each aggressor radio, based on information received from other radios, configures the root clock frequency of its RX and/or TX chain clock generation circuits.

Abstract: A timing estimation mechanism operative to generate an oversampling clock signal for a large range of reference clock frequencies without requiring use of a PLL. The oversampling timing mechanism generates appropriate timing instances, typically for the purpose of sampling a received data signal in a digital communications system, without requiring a specific external clock source but rather by utilizing a clock source having any arbitrary frequency. The mechanism of the present invention is especially suited for use in applications where a specific external clock source (e.g., integer multiple of the data rate) is not available and wherein the implications of the use of a PLL cannot be tolerated. The oversampling clock estimation mechanism generates a clock signal which may be unevenly distributed over the symbol period, but whereby on average, the correct number of samples is produced over a specific time duration.