Patents by Inventor Rong-Chang Feng

Rong-Chang Feng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8026603
    Abstract: An interconnect structure of an integrated circuit and manufacturing method therefore are provided, relating to an interconnect structure of flexible packaging. The interconnect structure includes a first and a second conductive pads. A plurality of tiny and conductive first pillars is respectively formed on the first and second pads. With different densities and thicknesses of the first and second pillars, a contact strength can be generated when the pillars interconnecting with each other, such that the pillars are connected closely. Furthermore, the interconnect structure can also be used to connect with fibers made of conductive materials. Moreover, the higher the density of the pillars, the stronger the contact strength. And, electronic substrates and active or passive electronic elements can be stuck on the other side of each pad. Therefore, the interconnect structure can maintain flexibility and have high reliability without being enhanced by any thermosetting polymer.
    Type: Grant
    Filed: April 21, 2006
    Date of Patent: September 27, 2011
    Assignee: Industrial Technology Research Institute
    Inventors: Yung-Yu Hsu, Chih-Yuan Cheng, Shyi-Ching Liau, Min-Lin Lee, Ra-Min Tain, Rong-Chang Feng
  • Patent number: 7754599
    Abstract: A structure for reducing stress for vias and a fabricating method thereof are provided. One or more wires or vias in the thickness direction are enframed with the use of a stress block in a lattice structure to be isolated from being directly contacted with the major portion of insulating materials with a high coefficient of thermal expansion. Thus, the shear stress resulting from temperature loading can be blocked or absorbed by the stress block.
    Type: Grant
    Filed: February 17, 2009
    Date of Patent: July 13, 2010
    Assignee: Industrial Technology Research Institute
    Inventors: Yung-Yu Hsu, Rong-Chang Feng, Ra-Min Tain, Shyi-Ching Liau, Ji-Cheng Lin, Shan-Pu Yu, Shou-Lung Chen, Chih-Yuan Cheng
  • Publication number: 20090156001
    Abstract: A structure for reducing stress for vias and a fabricating method thereof are provided. One or more wires or vias in the thickness direction are enframed with the use of a stress block in a lattice structure to be isolated from being directly contacted with the major portion of insulating materials with a high coefficient of thermal expansion. Thus, the shear stress resulting from temperature loading can be blocked or absorbed by the stress block.
    Type: Application
    Filed: February 17, 2009
    Publication date: June 18, 2009
    Inventors: Yung-Yu Hsu, Rong-Chang Feng, Ra-Min Tain, Shyi-Ching Liau, Ji-cheng Lin, Shan-Pu Yu, Shou-Lung Chen, Chih-Yuan Cheng
  • Patent number: 7545039
    Abstract: A structure for reducing stress for vias and a fabricating method thereof are provided. One or more wires or vias in the thickness direction are enframed with the use of a stress block in a lattice structure to be isolated from being directly contacted with the major portion of insulating materials with a high coefficient of thermal expansion. Thus, the shear stress resulting from temperature loading can be blocked or absorbed by the stress block.
    Type: Grant
    Filed: April 26, 2006
    Date of Patent: June 9, 2009
    Assignee: Industrial Technology Research Institute
    Inventors: Yung-Yu Hsu, Rong-Chang Feng, Ra-Min Tain, Shyi-Ching Liau, Ji-Cheng Lin, Shan-Pu Yu, Shou-Lung Chen, Chih-Yuah Cheng
  • Publication number: 20070128845
    Abstract: An interconnect structure of an integrated circuit and manufacturing method therefor are provided, relating to an interconnect structure of flexible packaging. The interconnect structure includes a first and a second conductive pads. A plurality of tiny and conductive first pillars is respectively formed on the first and second pads. With different densities and thicknesses of the first and second pillars, a contact strength can be generated when the pillars interconnecting with each other, such that the pillars are connected closely. Furthermore, the interconnect structure can also be used to connect with fibers made of conductive materials. Moreover, the higher the density of the pillars, the stronger the contact strength. And, electronic substrates and active or passive electronic elements can be stuck on the other side of each pad. Therefore, the interconnect structure can maintain flexibility and have high reliability without being enhanced by any thermosetting polymer.
    Type: Application
    Filed: April 21, 2006
    Publication date: June 7, 2007
    Applicant: Industrial Technology Research Institute
    Inventors: Yung-Yu Hsu, Chih-Yuan Chen, Shyi-Ching Liau, Min-Lin Lee, Ra-Min Tain, Rong-Chang Feng
  • Publication number: 20070108572
    Abstract: A structure for reducing stress for vias and a fabricating method thereof are provided. One or more wires or vias in the thickness direction are enframed with the use of a stress block in a lattice structure to be isolated from being directly contacted with the major portion of insulating materials with a high coefficient of thermal expansion. Thus, the shear stress resulting from temperature loading can be blocked or absorbed by the stress block.
    Type: Application
    Filed: April 26, 2006
    Publication date: May 17, 2007
    Inventors: Yung-Yu Hsu, Rong-Chang Feng, Ra-Min Tain, Shyi-Ching Liau, Ji-Cheng Lin, Shan-Pu Yu, Shou-Lung Chen, Chih-Yuah Cheng
  • Patent number: 7004642
    Abstract: The opto-electrical module packaging installs opto-electrical devices on a conductive leadframe to form an opto-electrical module. The opto-electrical module is then packaged using a molding packaging means, forming a transparent plastic base. The transparent plastic base is installed with a convergent lens to focus light. The leadframe has a plurality of pins and is mounted on the circuit board by soldering. This forms a packaging structure without bare pins exposed to the environment. In addition, the leadframe has a precision alignment structure extending outward as the alignment mechanism when assembled with a fiber connector. The precision packaging procedure provides a precision alignment of the converging lens and the opto-electrical devices at the same time.
    Type: Grant
    Filed: February 11, 2003
    Date of Patent: February 28, 2006
    Assignee: Industrial Technology Research Institute
    Inventors: Wen-Yan Chen, Rong-Chang Feng, Chun-Kai Liu
  • Publication number: 20030161367
    Abstract: The opto-electrical module packaging installs opto-electrical devices on a conductive leadframe to form an opto-electrical module. The opto-electrical module is then packaged using a molding packaging means, forming a transparent plastic base. The transparent plastic base is installed with a convergent lens to focus light. The leadframe has a plurality of pins and is mounted on the circuit board by soldering. This forms a packaging structure without bare pins exposed to the environment. In addition, the leadframe has a precision alignment structure extending outward as the alignment mechanism when assembled with a fiber connector. The precision packaging procedure provides a precision alignment of the converging lens and the opto-electrical devices at the same time.
    Type: Application
    Filed: February 11, 2003
    Publication date: August 28, 2003
    Inventors: Wen-Yan Chen, Rong-Chang Feng, Chun-Kai Liu