Abstract: A programmable clock deskewer generates an output clock with minimal clock skew. This is accomplished by means of a single series path coupling the input clock to the output clock. The programmable clock deskewer includes: an output clock generator, responsive to the input clock and control information, to generate the deskewed output clock; and a controller, responsive to the input clock, to generate the control information for controlling the frequency of the deskewed output clock. The programmable clock deskewer may be used to implement a clock tree with various clock outputs for a system on chip integrated circuit.

Abstract: A programmable clock deskewer generates an output clock with minimal clock skew. This is accomplished by means of a single series path coupling the input clock to the output clock. The programmable clock deskewer includes: an output clock generator, responsive to the input clock and control information, to generate the deskewed output clock; and a controller, responsive to the input clock, to generate the control information for controlling the frequency of the deskewed output clock. The programmable clock deskewer may be used to implement a clock tree with various clock outputs for a system on chip integrated circuit.

Abstract: A data handling method is provided for handling digitized data through compression/decompression and utilization. By this method, the original digitized data are concurrently compressed into a first set of compressed data through a low-compression-rate compression process and a second set of compressed data through a high-compression-rate compression process. Then, the first and second sets of compressed data are transferred together to an information processing unit, such as a personal computer. At the personal computer, the first set of compressed data are decompressed to obtain a set of decompressed data representing the original digitized data for output of the original digitized data at an output device, while the second set of compressed data remain in compressed form for storage and further transfer. Since the information processing unit needs to perform just a simple decompression process to decompress the low-compression-rate set of compressed data, the overall system efficiency can be increased.

Abstract: An apparatus is disclosed to convert a non-interlaced computer graphics signal which consists of contiguous scan lines into an interlaced video signal which alternately consists of even fields and odd fields. The converting apparatus includes a receiving means, a low-pass filter and a line buffer. The receiving means sequentially receives a scan line. The line buffer stores the brightness signals of the first and the second scan lines before the received scan line. And the low-pass filter receives the sequential contiguous scan lines from the line buffer and the displaying scan line, weights the brightness signals of these scan lines and outputs the scan lines with the weighted brightness signal and a halved refresh rate to serve as the even field and the odd field of the interlace video signal.

Abstract: An image-processing apparatus for controlling the display of a plurality of overlapped image data. The image-processing apparatus includes a control key generator, an overlay control register, and two multiplexers. The control key generator generates a plurality of control keys according to the drawing position on the monitor screen. Each control key defines two display areas on the monitor screen. The combinations of these display areas on the monitor screen thus define a plurality of overlapped display areas. The overlay control register stores display model data, each corresponding to an overlapped display area and representing the image data type of that overlapped display area. A first selector retrieves the display model data of the overlapped display areas from the overlay control register by using the control keys. A second selector uses the display model data obtained from the first selector to select the corresponding image data.