Abstract: A semiconductor memory device includes an M-by-N memory array having a number M of complete words, each of the complete words having a number N of bits. The memory array further has M word lines to address the M complete words, and N bit lines to access the N bits. The number N has a number p of integer factors. The memory array can be configured to operate in p different operating modes, where the bits of the complete words are rearranged into at least one sub-word formed as a bit group. An auxiliary address decoder, a mode selector, an auxiliary address router and an input data router cooperate with an input buffer portion of an input/output circuit to enable routing of input data bits from input data lines of an input data bus to a selected sub-word of the memory array.

Abstract: To configure a semiconductor memory device for presetting to a particular value without the need to write into each cell of a memory cell array, at least one controller is provided to address the array. The controller is responsive to preset, write and read control signals, and determines whether to keep an asserted state on a corresponding address select line of the array, or to force the corresponding address select line to a non-asserted state. Within the controller, at least one flag register is employed to indicate that a write operation has occurred for a corresponding word of the array. The flag register can be reset by means of the preset control signal. The controller will keep the asserted state on the corresponding address select line whenever the write control signal is asserted, and force the corresponding address select line to the non-asserted state when the read control signal is asserted and the corresponding address is not flagged.

Abstract: In a method and system for dynamic data encryption, a source data provider is used to provide a plurality of source data segments, while a segment header generator is employed to generate a plurality of segment headers that correspond respectively to the source data segments. Each of the segment headers includes a start code to indicate the start of the corresponding one of the data segments, a scrambling type to identify a selected one of at least two scrambling algorithms available for use when scrambling the corresponding one of the data segments, and a key word to be used during the scrambling of the corresponding one of the data segments. Each of the segment headers is placed before the corresponding one of the data segments, and each of the source data segments is scrambled according to the scrambling type and the key word identified in the corresponding one of the segment headers to obtain an encrypted data stream.

Abstract: In a method and apparatus for reducing the number of matrix operations when converting digitized RGB color space signals to digitized YCbCr color space signals, at least two color difference signals, each being in terms of any two of the digitized RGB color space signals, are generated before performing first, second, third and fourth matrix multiplication operations of the color difference signals. The first and second matrix multiplication operations have first and second results to be used in conversion for the digitized Y color space signal. The third matrix multiplication operation has a third result to be used in conversion for the digitized Cb color space signal. The fourth matrix multiplication operation has a fourth result to be used in conversion for the digitized Cr color space signal.

Abstract: In a method and apparatus for converting digitized luminance-chrominance color space signals to digitized RGB color space signals, a first combining unit generates a plurality of predetermined linear combinations of the chrominance color space signals received by a multiplexed multiplication unit which includes no more than two look-up tables that contain digitized transformation values for performing matrix multiplications of the linear combinations of the chrominance color space signals. A second combining unit linearly combines the digitized transformation values outputted by the multiplexed multiplication unit and a predetermined binary combination of the luminance color space signal in a first predetermined manner to generate three RGB color combination signals. A third combining unit linearly combines the RGB color combination signals in a second predetermined manner to obtain the RGB color space signals.

Abstract: A method for generating an output signal of desired polarity from an input periodical signal of frequency f1 via a clock signal of frequency f2, wherein f2 is substantially greater than f1, is provided. The input periodical signal includes a cyclic duration T1 of a first logic state and duration T2 of a second logic state. The method includes the steps of (1) counting pulses N of the clock signal during T1; (2) counting pulses M of the clock signal during T2; (3) generating the output signal by inverting the input periodical signal as M being larger than N and an activated state of select signal are determined.

Abstract: An array of static random access memory (SRAM) cells is configured for presetting to a particular value without the need to write to each cell in the array. Address line controllers are provided which are responsive to preset, read, and write signals. If a write control signal is asserted, the address line controllers maintain an asserted state on their address lines, so that a subsequent read cycle will output the written memory cell contents. However, if the memory cells in the array have not been written to, the address line controllers deassert their address lines, and simultaneously enable preset setting cells, so that a subsequent read cycle will output the logic state of the setting cells, rather than the contents of the array memory cells.

Abstract: In a method and apparatus for reducing the number of matrix operations when converting digitized RGB color space signals to digitized YCbCr color space signals, at least two color difference signals, each being in terms of any two of the digitized RGB color space signals, are generated before performing first, second, third and fourth matrix multiplication operations of the color difference signals. The first and second matrix multiplication operations have first and second results to be used in conversion for the digitized Y color space signal. The third matrix multiplication operation has a third result to be used in conversion for the digitized Cb color space signal. The fourth matrix multiplication operation has a fourth result to be used in conversion for the digitized Cr color space signal.

Abstract: An apparatus is used to process an original digital image to obtain a uniformly scaled desired digital image, the original digital image having a number (N) of successive original image data while the desired digital image has a number (M) of successive desired image data. When (M) is greater than (N), linear interpolation of (n)th and (n+1)th ones of the original image data is performed to produce a residual interpolated image data inserted therebetween when division of (M-N) by (N-1) results in a remainder (S) and when (n) is a minimum number which meets a condition (n+1)*(S).gtoreq.(s)*(N), wherein (s) ranges from 1 to (S). When (M) is less than (N), an address generator controls a memory to output selected ones of the original image data. A succeeding original image data outputted by the memory is offset from an immediately preceding original image data outputted thereby by a number (V) or by a number (V+1), the number (V) being equal to a quotient that results from division of (N) by (M).

Abstract: A method for gradually adjusting intensity of a color component of pixels of successive images in a video data includes the steps of: a) providing an offset value; b) adding the offset value to the color component of each of the pixels of the successive images of the video data to generate an adjusted color component; c) setting a frequency factor indicative of times of adjustment of the offset value, the frequency factor corresponding to a number of the successive images per adjustment of the offset value; and d) adjusting the offset value in a predetermined manner in accordance with the frequency factor. An apparatus for gradually adjusting intensity of the color component is also disclosed.

Abstract: A display control apparatus is provided to generate a scaled video output overlaid onto a computer graphics output. The display control apparatus includes a timing generator, adapted to receive a horizontal synchronization signal of the computer graphics output and the pixel number of horizontal scan line of the scaled video output, for generating a pixel clock of scaled video output and a horizontal lock signal; a scaling buffer, storing a video digital pixel data and having an output port generating the scaled video output, responsive to the pixel clock of scaled video output; an overlay controller, coupled to a controller bus and receiving an analog pixel data of the computer graphics output and, responsive to the pixel clock of scaled video output, the horizontal lock signal and a vertical synchronization signal of the computer graphics output, for overlaying the scaled video output onto the computer graphics output.

Abstract: The present invention is related to an apparatus for digital video format conversion for a decompressed digital video data outputted from a decompressor, which includes a video interpolation device processing the decompressed digital video data by way of on-the-fly interpolating and filtering procedures to obtain an interpolated and filtered digital video data, and a color space converter electrically connected to the video interpolation device for converting the interpolated and filtered digital video data processed by the on-the-fly interpolating and filtering procedures from a first color space into a second one to complete the digital video format conversion. The present apparatus processes the decompressed digital video data by way of on-the-fly interpolating and filtering procedures and therefore the resolution of an original frame can be shown on a computer monitor to obtain a good frame quality.

Abstract: An apparatus is used to process an original digital image to obtain a uniformly scaled desired digital image, the original digital image having a number (N) of successive original image data while the desired digital image has a number (M) of successive desired image data. When (M) is greater than (N), linear interpolation of (n)th and (n+1)th ones of the original image data is performed to produce a residual interpolated image data inserted therebetween when division of (M-N) by (N-1) results in a remainder (S) and when (n) is a minimum number which meets a condition (n+1)*(S).gtoreq.(s)*(N), wherein (s) ranges from 1 to (S). When (M) is less than (N), an address generator controls a memory unit to output selected ones of the original image data. A succeeding original image data outputted by the memory unit is offset from an immediately preceding original image data outputted thereby by a number (V) or by a number (V+1), the number (V) being equal to a quotient that results from division of (N) by (M).

Abstract: A method and apparatus for performing color space conversion between digitized YCbCr components and digitized RGB components uses a color lookup table unit which is provided with transformation component values based on a selected one of two sets of conversions. A plurality of adders are coupled to the lookup table unit so as to receive the outputs thereof and generate individual color components of converted space by adding the transformation component values corresponding to each of the individual color components of converted space relative to the color components of original space.

Abstract: The invention inputs a single timing clock. Through procedure of mode setting, the invention generates the required timings corresponding to the display mode selected. In the invention, a programmable mode register, a mode decoder, a pixel timing generator, a horizontal timing generator, a vertical timing generator, a composite timing generator, AND gate, EXCLUSIVE NOR gate, and a selector are provided. The invention may generate the required timings for NTSC interlace mode, NTSC non-interlace mode, PAL interlace mode, PAL non-interlace mode, VGA 60 Hz progressive mode and VGA 50 Hz progressive mode.

Abstract: A discrete cosine transform (DCT) apparatus, capable of generating one-dimensional and two-dimensional DCT and inverse DCT results, uses six-stage DCT/IDCT fast algorithms to process a sequence of input data of an 8.times.8 data block. Each of the different stages of the DCT/IDCT fast algorithms involves a number of butterfly operations, which can be performed by a butterfly operation unit of the DCT apparatus, or a number of intrinsic multiplications, a number of post-addition multiplication operations, or a number of post-multiplication subtraction operations, all of which can be performed by a multiplication operation unit. A control unit of the DCT apparatus permits the use of a single butterfly operation unit and a single multiplication operation unit to perform the different stages of the DCT/IDCT fast algorithms. The results of each stage of the DCT/IDCT fast algorithms are stored in a data register unit of the DCT apparatus to serve as inputs for the succeeding stages of the DCT/IDCT fast algorithms.

Abstract: An apparatus for showing a digitized NTSC-encoded video signal on an NTSC or PAL color television screen includes a system memory unit for storing the digitized video signal therein. A sync generator provides NTSC or PAL horizontal and vertical sync signals depending upon the type of color television screen in use. A sync delay and shading circuit provides an appropriate delay to the PAL horizontal and vertical sync signals when a PAL color television screen is in use. The horizontal and vertical sync signals control the cathode ray tube (CRT) unit to access the digitized video image in the system memory unit. The sync delay and shading circuit also disables the CRT control unit, a color burst generator, a (B-Y) and an (R-Y) color difference digital-to-analog (D/A) converter and a luminance and sync D/A converter during a 100 scan line period in which no video image is being displayed when the PAL color television screen is in use.