Abstract: A universal translator control system for remote control of a robot with a joystick. The system includes a calculation unit for storing translation logic, a control access interface unit electrically connected to the calculation unit, and a joystick which is operated to generate signals that have at least an X-coordinate value, X-direction rotation value, Y-coordinate value, Y-direction rotation value, Z-coordinate value, and Z-direction rotation value. Specifically, a robotic access interface unit is electrically connected to the calculation unit and the robot, whereby the translation logic in the calculation unit is used to translate the signals generated by the joystick as a translated X coordinate value, translated X-direction rotation value, translated Y coordinate value, translated Y-direction rotation value, translated Z coordinate value, and translated Z-direction rotation value, which are transmitted to the robot.

Abstract: A multi-threshold storage device and method is disclosed herein. The device comprises at least one hard disc drive (HDD), at least one solid state drive (SSD), and a controller electrically connected with HDD and SSD. The controller determines whether to store a file in HDD or SSD according to whether the read/write (r/w) count of the file exceeds a preset r/w count, whether the storage space occupied by the file exceeds a preset storage space, and whether the file is a popular file. The present invention uses multiple thresholds to configure storage positions of files, improve the economical efficiency of file storage and raise the overall performance of a server system.

Abstract: A segmental allocation method of expanding RISC processor register includes the steps of a) setting an instruction format of the RISC processor, the destination register field being set having 6 bits to correspond to 64 registers and at least one source register field having at least 4 bits to correspond to at least 16 registers; b) providing two solutions to the problem resulting from that the instruction format in the step a) goes beyond range under some circumstances; and c) setting a register segment allocation algorithm having the steps of c1) providing and grouping a plurality of pseudo registers; c2) prioritizing the pseudo registers in each of the groups; c3) combining the groups pursuant to the priorities thereof; and c4) locating the physical register of lowest computational cost.

Abstract: A method for synthesizing Sigma-Delta Modulator, which selects at least a system configuration and parameters, substitute a noise transfer formula into said system configuration to obtain coefficients. Using a least-square method to obtain a stability equation, and calculating an ideal performance of said system configuration based on said parameters and stability equation. Substitute the coefficients into non-ideal effect models, and acquire the circuit specification of an operation amplifier in said system configuration in a hierarchic approach to calculate the circuit performance of the operation amplifier. Determine whether said circuit specification of said operation amplifier has a solution based on related specification equation. If an answer is positive, calibrate length and width of transistors in said operation amplifier, until it meets the requirements of said circuit specification.

Abstract: A segmental allocation method of expanding RISC processor register includes the steps of a) setting an instruction format of the RISC processor, the destination register field being set having 6 bits to correspond to 64 registers and at least one source register field having at least 4 bits to correspond to at least 16 registers; b) providing two solutions to the problem resulting from that the instruction format in the step a) goes beyond range under some circumstances; and c) setting a register segment allocation algorithm having the steps of c1) providing and grouping a plurality of pseudo registers; c2) prioritizing the pseudo registers in each of the groups; c3) combining the groups pursuant to the priorities thereof; and c4) locating the physical register of lowest computational cost.

Abstract: The present invention discloses a power-aware compiling method, wherein the power model of an application program are established via building and analyzing the control flow chart and the data flow chart of the application program; each functional unit of the application program is assigned a power mode; a judgment is undertaken to determine whether the idle functional units are independent; if none dependency exists between those idle function units, the program codes of the same idle function units are merged into a new basic block, and the idle functional units are turned off for saving power; each new basic block is assigned an appropriate power mode; the basic blocks with the same power modes are merged to reduce the transitions between different power modes; thus, the power consumed by changing voltage or frequency can be decreased.

Abstract: A RISC processor register expansion method is disclosed to include the steps of: a) designing an instruction format having multiple register fields to have the total bits consumed by the register fields to be designed into two bits combinations respectively corresponding to two register banks, wherein the first bits combination has 8 bits of which the value of the 1st˜7th bits is adapted to designate the location (0-127) of the first register field in one of the two register banks and the value of the 8th bit is adapted to designate which one of the two register banks the first register field is to be allocated, and the second bits combination has at least 2 bits; b) defining an operation instruction without exchangeability to be an inverse operation instruction; and c) designing a register allocation algorithm to pick up one respective operand variable from each of the two register banks and to join the two operand variables into a node and using the relationship between nodes to run computation and to deter

Abstract: The present invention discloses a sigma-delta modulator architecture capable of automatically improving dynamic range and a method for the same. Based on the concept that different dynamic ranges of a sigma-delta modulator can be obtained via adjusting the signal power gain thereof, the present invention provides a novel algorithm to implement an automation program. The present invention finds out several sets of dynamic-range curves to improve the overall dynamic range. Via a high-level sigma-delta modulator architecture, the present invention can calculate the required feedforward coefficients. Further, the present invention install in the sigma-delta modulator architecture with four additional components, including a peak detection unit, a comparator unit, a digital coefficient control unit and a switch unit, to dynamically detect the output of the sigma-delta modulator and dynamically modify the feedforward coefficient of the sigma-delta modulator.

Abstract: The present invention discloses a sigma-delta modulator architecture capable of automatically improving dynamic range and a method for the same. Based on the concept that different dynamic ranges of a sigma-delta modulator can be obtained via adjusting the signal power gain thereof, the present invention provides a novel algorithm to implement an automation program. The present invention finds out several sets of dynamic-range curves to improve the overall dynamic range. Via a high-level sigma-delta modulator architecture, the present invention can calculate the required feedforward coefficients. Further, the present invention install in the sigma-delta modulator architecture with four additional components, including a peak detection unit, a comparator unit, a digital coefficient control unit and a switch unit, to dynamically detect the output of the sigma-delta modulator and dynamically modify the feedforward coefficient of the sigma-delta modulator.

Abstract: The present invention provides a method and system for processing an instruction set, which can be applied to compress the operation part of a sequence of instructions in the instruction set and to perform the corresponding decompression. Upon the compression, the sequence of instructions is divided into a operation part and a register part, then recursively compress consecutive instructions with two operation codes that emerge repeatedly in the sequence of instructions until no further compression can be performed. The compression leads to form a binary tree which constitutes of nodes corresponding to the original operation codes or the ones derived from them in the recursive compression process. Furthermore, a pre-fetch mechanism is used in the present invention to promote the performance upon decompression.

Abstract: The present invention discloses a power-aware compiling method, wherein the power model of an application program are established via building and analyzing the control flow chart and the data flow chart of the application program; each functional unit of the application program is assigned a power mode; a judgment is undertaken to determine whether the idle functional units are independent; if none dependency exists between those idle function units, the program codes of the same idle function units are merged into a new basic block, and the idle functional units are turned off for saving power; each new basic block is assigned an appropriate power mode; the basic blocks with the same power modes are merged to reduce the transitions between different power modes; thus, the power consumed by changing voltage or frequency can be decreased.

Abstract: The present invention provides a method and system for processing an instruction set, which can be applied to compress the operation part of a sequence of instructions in the instruction set and to perform the corresponding decompression. Upon the compression, the sequence of instructions is divided into a operation part and a register part, then recursively compress consecutive instructions with two operation codes that emerge repeatedly in the sequence of instructions until no further compression can be performed. The compression leads to form a binary tree which constitutes of nodes corresponding to the original operation codes or the ones derived from them in the recursive compression process. Furthermore, a pre-fetch mechanism is used in the present invention to promote the performance upon decompression.