Abstract: A semiconductor device includes: a substrate; a first insulating film disposed on the substrate and having at least one via; and a second insulating film disposed on the first insulating film. The semiconductor device further includes: a first adhesion layer disposed on the first insulating film; a first conductive structure disposed in the at least one via and having an extended portion extending to a top surface of the first insulating film; and a second adhesion layer disposed on the first conductive structure. The first adhesion layer covers at least a part of a bottom surface of the extended portion, and the second adhesion layer covers at least a part of a top surface of the first conductive structure.

Abstract: A HEMT structure includes a compound semiconductor substrate, a gate electrode, a source electrode, a drain electrode, a first metal pillar, a second metal pillar, a dielectric layer, and a metal layer. The gate electrode is disposed on the compound semiconductor substrate. The source electrode is disposed on the compound semiconductor substrate at a first side of the gate electrode. The drain electrode is disposed on the compound semiconductor substrate at a second side of the gate electrode. The first metal pillar is disposed on the source electrode. The second metal pillar is disposed on the drain electrode. The dielectric layer is disposed on the compound semiconductor substrate. The dielectric layer surrounds the gate electrode, the first metal pillar, and the second metal pillar. The metal layer is disposed on the dielectric layer. The metal layer straddles the gate electrode, the first metal pillar, and the second metal pillar.

Abstract: A semiconductor chip includes an active device and a passive device formed over a substrate. A passivation layer covers the active device and the passive device. A barrier structure surrounds the active device. A ceiling layer is formed across the barrier structure over the active device. The ceiling layer has an opening exposing the barrier structure.

Abstract: A transistor device includes a substrate and a gate structure. The gate structure is disposed on the substrate. The gate structure includes a first metal layer and a refractory metal layer disposed on the first metal layer, wherein the first metal layer is disconnected and the refractory metal layer is disconnected.

Abstract: A heterojunction bipolar transistor includes an emitter layer on a base layer on a collector layer on an upper sub-collector layer over a bottom sub-collector layer, a first dielectric film over the bottom sub-collector layer, the base layer and the emitter layer, a base electrode on the first dielectric film, electrically connected to the base layer through at least one first via hole in the first dielectric film, a second dielectric film on the first dielectric film and the base electrode, and a conductive layer on the second dielectric film, with conductive layer electrically connected to base electrode through a second via hole disposed in the second dielectric film, first dielectric film between the base electrode and first sidewall of a stack including the base layer and the collector layer, and second via hole laterally separated from the base layer.

Abstract: A HEMT structure includes a compound semiconductor substrate, a gate electrode, a source electrode, a drain electrode, a first metal pillar, a second metal pillar, a dielectric layer, and a metal layer. The gate electrode is disposed on the compound semiconductor substrate. The source electrode is disposed on the compound semiconductor substrate at a first side of the gate electrode. The drain electrode is disposed on the compound semiconductor substrate at a second side of the gate electrode. The first metal pillar is disposed on the source electrode. The second metal pillar is disposed on the drain electrode. The dielectric layer is disposed on the compound semiconductor substrate. The dielectric layer surrounds the gate electrode, the first metal pillar, and the second metal pillar. The metal layer is disposed on the dielectric layer. The metal layer straddles the gate electrode, the first metal pillar, and the second metal pillar.

Abstract: A heterojunction bipolar transistor includes an emitter layer on a base layer on a collector layer on an upper sub-collector layer over a bottom sub-collector layer, a first dielectric film over the bottom sub-collector layer, the base layer and the emitter layer, a base electrode on the first dielectric film, electrically connected to the base layer through at least one first via hole in the first dielectric film, a second dielectric film on the first dielectric film and the base electrode, and a conductive layer on the second dielectric film, with conductive layer electrically connected to base electrode through a second via hole disposed in the second dielectric film, first dielectric film between the base electrode and first sidewall of a stack including the base layer and the collector layer, and second via hole laterally separated from the base layer.

Abstract: A heterojunction bipolar transistor includes an emitter layer on a base layer on a collector layer on an upper sub-collector layer over a bottom sub-collector layer, a first dielectric film over the bottom sub-collector layer, the base layer and the emitter layer, a base electrode on the first dielectric film, electrically connected to the base layer through at least one first via hole in the first dielectric film, a second dielectric film on the first dielectric film and the base electrode, and a conductive layer on the second dielectric film, with conductive layer electrically connected to base electrode through a second via hole disposed in the second dielectric film, first dielectric film between the base electrode and first sidewall of a stack including the base layer and the collector layer, and second via hole laterally separated from the base layer.

Abstract: A heterojunction bipolar transistor, comprising an elongated base mesa, an elongated base electrode, two elongated emitters, an elongated collector, and two elongated collector electrodes. The elongated base electrode is formed on the base mesa along the long axis of the base mesa, and the base electrode has a base via hole at or near the center of the base electrode. The two elongated emitter are formed on the base mesa respectively at two opposite sides of the base electrode, and each of two emitters has an elongated emitter electrode formed on the emitter. The elongated collector is formed below the base mesa. The two elongated collector electrodes are formed on the collector respectively at two opposite sides of the base mesa.

Abstract: A protective cover for an acoustic wave device and a fabrication method thereof, for protecting an acoustic wave device having a resonant area during a packaging operation so as to avoid molding compound flowing onto the resonant area of the acoustic wave device. The fabrication method comprises: defining a sacrificial area on the acoustic wave device; forming a sacrificial layer on the sacrificial area; covering a metal covering layer on the sacrificial layer and connecting a bottom rim of the metal covering layer to the acoustic wave device and forming an opening between the bottom rim of the metal covering layer and the acoustic wave device; and removing the sacrificial layer to form a cavity between the metal covering layer and the resonant area by using a chemical solution, wherein the chemical solution enters from the opening between the metal covering layer and the acoustic wave device.

Abstract: A layout method for compound semiconductor integrated circuits, comprising following steps of: forming a first metal layer within a first circuit layout area which intersects with a second circuit layout area at an intersection area on a compound semiconductor substrate; defining an adjacent crossover area including said intersection area and a peripheral adjacent area thereof; a first dielectric area located within said adjacent crossover area and intersected with at least part of said intersection area; forming a first dielectric block within said first dielectric area or forming said first dielectric block within said first dielectric area and a second dielectric block outside said first dielectric area, the thickness of said second dielectric block is no greater than and the thickness of at least part of said second dielectric block is smaller than the thickness of said first dielectric block; forming a second metal layer within said second circuit layout area.

Abstract: A heterojunction bipolar transistor, comprising an elongated base mesa, an elongated base electrode, two elongated emitters, an elongated collector, and two elongated collector electrodes. The elongated base electrode is formed on the base mesa along the long axis of the base mesa, and the base electrode has a base via hole at or near the center of the base electrode. The two elongated emitter are formed on the base mesa respectively at two opposite sides of the base electrode, and each of two emitters has an elongated emitter electrode formed on the emitter. The elongated collector is formed below the base mesa. The two elongated collector electrodes are formed on the collector respectively at two opposite sides of the base mesa.

Abstract: A heterojunction bipolar transistor, comprising an elongated base mesa, an “H” shaped emitter, two base electrodes, an elongated collector, and two elongated collector electrodes. The “H” shaped emitter is formed on the base mesa and has two parallel bars connected by a cross-bar. Two elongated emitter electrodes are formed respectively on the two parallel bars of the “H” shaped emitter. The “H” shaped emitter has two recesses respectively on two opposite sides of the cross-bar between the two parallel bars. The two base electrodes are formed on the base mesa respectively at the two recesses of the “H” shaped emitter, each of which has a base via hole near a center of the base mesa. The elongated collector is formed below the base mesa. The two elongated collector electrodes are formed on the collector respectively at two opposite sides of the base mesa.

Abstract: A protective cover for an acoustic wave device and a fabrication method thereof, for protecting an acoustic wave device having a resonant area on a surface of a substrate during a packaging operation so as to avoid molding compound flowing onto the resonant area of the acoustic wave device, wherein at least one electrical device is provided on the surface of the substrate and the at least one electrical device includes a temperature sensor. The acoustic wave device protection structure comprising: a metal covering layer, having a concave surface and a bottom rim, the bottom rim connected to the acoustic wave device and forming at least one opening between the bottom rim and the acoustic wave device, and the concave surface covering over the resonant area to form a cavity between the concave surface and the resonant area.

Abstract: A layout method for compound semiconductor integrated circuits, comprising following steps of: forming a first metal layer within a first circuit layout area which intersects with a second circuit layout area at an intersection area on a compound semiconductor substrate; defining an adjacent crossover area including said intersection area and a peripheral adjacent area thereof; a first dielectric area located within said adjacent crossover area and intersected with at least part of said intersection area; forming a first dielectric block within said first dielectric area or forming said first dielectric block within said first dielectric area and a second dielectric block outside said first dielectric area, the thickness of said second dielectric block is no greater than and the thickness of at least part of said second dielectric block is smaller than the thickness of said first dielectric block; forming a second metal layer within said second circuit layout area.

Abstract: A protective cover for an acoustic wave device and a fabrication method thereof, for protecting an acoustic wave device having a resonant area during a packaging operation so as to avoid molding compound flowing onto the resonant area of the acoustic wave device. The fabrication method comprises: defining a sacrificial area on the acoustic wave device; forming a sacrificial layer on the sacrificial area; covering a metal covering layer on the sacrificial layer and connecting a bottom rim of the metal covering layer to the acoustic wave device and forming an opening between the bottom rim of the metal covering layer and the acoustic wave device; and removing the sacrificial layer to form a cavity between the metal covering layer and the resonant area by using a chemical solution, wherein the chemical solution enters from the opening between the metal covering layer and the acoustic wave device.

Abstract: A heterojunction bipolar transistor, comprising an elongated base mesa, an “H” shaped emitter, two base electrodes, an elongated collector, and two elongated collector electrodes. The “H” shaped emitter is formed on the base mesa and has two recesses respectively on two opposite sides of the “H” shape, and the emitter has two elongated emitter electrodes formed on the “H” shaped emitter. The two base electrodes are formed on the base mesa respectively at the two recesses of the “H” shaped emitter, and each of the base electrodes has a base via hole at or near the center of the base mesa. The elongated collector is formed below the base mesa. The two elongated collector electrodes are formed on the collector respectively at two opposite sides of the base mesa.

Abstract: A heterojunction bipolar transistor, comprising an elongated base mesa, an elongated base electrode, two elongated emitters, an elongated collector, and two elongated collector electrodes. The elongated base electrode is formed on the base mesa along the long axis of the base mesa, and the base electrode has a base via hole at or near the center of the base electrode. The two elongated emitter are formed on the base mesa respectively at two opposite sides of the base electrode, and each of two emitters has an elongated emitter electrode formed on the emitter. The elongated collector is formed below the base mesa. The two elongated collector electrodes are formed on the collector respectively at two opposite sides of the base mesa.

Abstract: A monolithic compound semiconductor structure is disclosed. The monolithic compound semiconductor structure comprises a substrate, an n-type FET epitaxial structure, an n-type etching-stop layer, a p-type insertion layer, and an npn HBT epitaxial structure, and it can be used to form an FET, an HBT, or a thyristor.

Abstract: An integrated structure of compound semiconductor devices is disclosed. The integrated structure comprises from bottom to top a substrate, a first epitaxial layer, an etching-stop layer, a second epitaxial layer, a sub-collector layer, a collector layer, a base layer, and an emitter layer, in which the first epitaxial layer is a p-type doped layer, the second epitaxial layer is an n-type graded doping layer with a gradually increased or decreased doping concentration, and the sub-collector layer is an n-type doped layer. The integrated structure can be used to form an HBT, a varactor, or an MESFET.