Patents by Inventor Rong Hsu

Rong Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150278420
    Abstract: A method embodiment includes identifying, by a processor, an empty region in an integrated circuit (IC) layout, wherein the empty region is a region not including any active fins. The method further includes providing a standard dummy fin cell and forming an expanded dummy fin cell. The standard dummy fin cell includes a plurality of partitions. The expanded dummy fin cell is larger than the standard dummy fin cell, and the expanded dummy fin cell includes integer multiples of each of the plurality of partitions. The empty region is filled with a plurality of dummy fin cells, wherein the plurality of dummy fin cells includes the expanded dummy fin cell. The plurality of dummy fin cells is implemented in an IC.
    Type: Application
    Filed: June 15, 2015
    Publication date: October 1, 2015
    Inventors: Li-Sheng Ke, Jia-Rong Hsu, Hung-Lung Lin, Wen-Ju Yang
  • Patent number: 9147029
    Abstract: A method embodiment includes identifying, by a processor, an empty region in an integrated circuit (IC) layout, wherein the empty region is a region not including any active fins. The method further includes providing a standard dummy fin cell and forming an expanded dummy fin cell. The standard dummy fin cell includes a plurality of partitions. The expanded dummy fin cell is larger than the standard dummy fin cell, and the expanded dummy fin cell includes integer multiples of each of the plurality of partitions. The empty region is filled with a plurality of dummy fin cells, wherein the plurality of dummy fin cells includes the expanded dummy fin cell. The plurality of dummy fin cells is implemented in an IC.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: September 29, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Sheng Ke, Jia-Rong Hsu, Wen-Ju Yang, Hung-Lung Lin
  • Publication number: 20140325466
    Abstract: A method embodiment includes identifying, by a processor, an empty region in an integrated circuit (IC) layout, wherein the empty region is a region not including any active fins. The method further includes providing a standard dummy fin cell and forming an expanded dummy fin cell. The standard dummy fin cell includes a plurality of partitions. The expanded dummy fin cell is larger than the standard dummy fin cell, and the expanded dummy fin cell includes integer multiples of each of the plurality of partitions. The empty region is filled with a plurality of dummy fin cells, wherein the plurality of dummy fin cells includes the expanded dummy fin cell. The plurality of dummy fin cells is implemented in an IC.
    Type: Application
    Filed: July 8, 2014
    Publication date: October 30, 2014
    Inventors: Li-Sheng Ke, Jia-Rong Hsu, Wen-Ju Yang, Hung-Lung Lin
  • Patent number: 8869090
    Abstract: A method embodiment includes identifying an empty region in an integrated circuit (IC) layout, wherein the empty region is a region not including any active fins and outside a minimum spacing boundary, applying a grid map over the empty region, wherein the grid map comprises a plurality of grids inside the empty region, and filling the empty region with a plurality of dummy fin cells by placing a dummy fin cell in each of the plurality of grids, wherein applying the grid map and filling the empty region is performed using a computer.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 21, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Sheng Ke, Min-Yuan Tsai, Jia-Rong Hsu, Hung-Lung Lin, Wen-Ju Yang
  • Publication number: 20140258961
    Abstract: A method embodiment includes identifying an empty region in an integrated circuit (IC) layout, wherein the empty region is a region not including any active fins and outside a minimum spacing boundary, applying a grid map over the empty region, wherein the grid map comprises a plurality of grids inside the empty region, and filling the empty region with a plurality of dummy fin cells by placing a dummy fin cell in each of the plurality of grids, wherein applying the grid map and filling the empty region is performed using a computer.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 11, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Sheng Ke, Min-Yuan Tsai, Jia-Rong Hsu, Hung-Lung Lin, Wen-Ju Yang
  • Publication number: 20140098081
    Abstract: A display device including an e-paper device and a power converter is provided. The e-paper device displays information. The power converter generates a plurality of output voltages respectively at a plurality of output terminals and provides the plurality of output voltages to the e-paper device. The power converter includes a transformer and a plurality of diodes. The transformer has a primary winding and a plurality of secondary windings. The diodes are electrically connected between the secondary windings and the output terminals for generating the output voltages, respectively.
    Type: Application
    Filed: December 11, 2013
    Publication date: April 10, 2014
    Applicant: Delta Electonics, Inc.
    Inventors: Ming-Chih CHIU, Wen-Pin LIU, Rong HSU
  • Patent number: 8560997
    Abstract: Among other things, one or more techniques for conditional cell placement are provided herein. In an embodiment, a conditional boundary is created for a first cell. For example, the conditional boundary enables the first cell to be placed relative to a second cell based on a conditional placement rule. In an embodiment, the first cell is placed in a first manner relative to the second cell based in a first scenario. In a second scenario, different than the first scenario, the first cell is placed in a second manner relative to the second cell. In this manner, conditional cell placement is provided, thus providing flexibility and improved layout efficiency with regard to semiconductor fabrication, for example.
    Type: Grant
    Filed: July 25, 2012
    Date of Patent: October 15, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ping-Lin Yang, Ming-Zhang Kuo, Cheng-Chung Lin, Jimmy Hsiao, Jia-Rong Hsu
  • Publication number: 20130136714
    Abstract: PEO-PPO-PEO polymers and vinyl monomers are used to prepare several block copolymers via consecutive atom transfer radical polymerization (ATRP). The block copolymers provide good delivery characteristics and can be used as a gene/drug delivery carrier for therapy and diagnosis.
    Type: Application
    Filed: August 10, 2012
    Publication date: May 30, 2013
    Applicant: KAOHSIUNG MEDICAL UNIVERSITY
    Inventors: Li-Fang Wang, Shih-Jer Huang, Zhi-Rong Hsu
  • Publication number: 20110288850
    Abstract: An electronic apparatus with a multi-mode interactive operation method is disclosed. The electronic apparatus includes a display unit, a selecting unit, a voice recognition unit and a control unit. The display unit displays a frame. The selecting unit selects an arbitrary area of the frame on the display unit. The voice recognition unit recognizes a voice signal as a control command. The control unit processes data according to the control command on the content of the arbitrary area selected. A multi-mode interactive operation method is disclosed herein as well.
    Type: Application
    Filed: March 10, 2011
    Publication date: November 24, 2011
    Applicant: DELTA ELECTRONICS, INC.
    Inventors: Jia-Lin SHEN, Tien-Ming HSU, Rong HSU, Yu-Kai CHEN, Rong-Chang LIANG
  • Publication number: 20110192235
    Abstract: A digital display module for a torsion wrench includes a housing sleeved on a shank of the torsion wrench. A microprocessor is disposed in the housing and includes a normal display model and an inverted display model therein, wherein the normal display model is provided for right-handed operator and the inverted display model is provided for left-handed operator. Multiple function keys are arranged on the periphery of the housing for selecting display models and inputting data. A display screen is mounted on the periphery of the housing and electrically connected to the microprocessor. The display screen is divided into a first display zone for showing numeral and a second display zone for showing scale ratio. A sensor is mounted on a torsion unit of the torsion wrench and electrically connected to the microprocessor for sensing the operating torsion and transmitting torsion data to the microprocessor.
    Type: Application
    Filed: September 21, 2010
    Publication date: August 11, 2011
    Applicant: TAKEN ETORQUE TECHNOLOGY CO., LTD.
    Inventor: Shu-Rong Hsu
  • Publication number: 20110084949
    Abstract: A display device including an e-paper device and a power converter is provided. The e-paper device displays information. The power converter generates a plurality of output voltages respectively at a plurality of output terminals and provides the plurality of output voltages to the e-paper device. The power converter includes a transformer and a plurality of diodes. The transformer has a primary winding and a plurality of secondary windings. The diodes are electrically connected between the secondary windings and the output terminals for generating the output voltages, respectively.
    Type: Application
    Filed: October 12, 2010
    Publication date: April 14, 2011
    Inventors: Ming-Chih Chiu, Wen-Pin Liu, Rong Hsu
  • Patent number: 6429132
    Abstract: A combination CMP-etch method for forming a thin planar layer over the surface of a device includes the steps of providing a substrate including a plurality of surface projections defining gaps therebetween, forming an etchable layer on the substrate, performing a CMP process on the etchable layer to form a planar layer having a first thickness in excess of 1,000 Angstroms, and etching the planar layer to a second thickness less than 1,000 Angstroms. In a particular method, the step of forming the etchable layer includes the steps of forming an etch resistant layer on the substrate, forming a fill layer on the etch-resistant layer, etching the fill layer to expose portions of the etch-resistant layer overlying the projections, and to leave a portion of the fill layer in the gaps, and forming the etchable layer on the exposed portions of the etch-resistant layer and the fill layer.
    Type: Grant
    Filed: December 23, 1998
    Date of Patent: August 6, 2002
    Assignee: Aurora Systems, Inc.
    Inventors: Jacob Daniel Haskell, Rong Hsu
  • Patent number: 6390483
    Abstract: A folding device for a scooter includes a base plate, a head tube, a handlebar stem, a support rod, and a support base. The support base includes a first side plate and a second side plate, an arcuate slide track defined in the first side plate, and a first locking hole and a second locking hole respectively defined in the second side plate. The support rod includes a transverse tube pivotally mounted between the first side plate and the second side plate and a receiving chamber located above the transverse tube for receiving a support tube. A pull rod is slidably mounted in the support tube and has a first end provided with an outer thread slidably mounted in the slide track and engaged with a pull knob and a second end provided with an enlarged head detachably received in the first locking hole or the second locking hole. A guard plate is mounted for supporting the support rod, and a retaining piece is pivotally mounted on the guard plate for retaining the support rod.
    Type: Grant
    Filed: July 19, 2000
    Date of Patent: May 21, 2002
    Assignees: Hao Yih Trading Co., Ltd., Zenital Inc.
    Inventors: Chen-Rong Hsu, Jenn-Jia Shu
  • Patent number: 6277748
    Abstract: A method for manufacturing a planar reflective light valve backplane includes the steps of providing a substrate (e.g., a reflective backplane) including a plurality of surface projections (e.g., pixel mirrors) defining gaps therebetween, forming an etch-resistant layer on the substrate, forming a fill layer on the etch resistant layer, and etching the fill layer to expose portions of the etch resistant layer overlying the projections, leaving a portion of the fill layer in the gaps. A particular method includes an optional step of forming a protective layer over the exposed portions of the etch-resistant layer and the fill layer. In another particular method, the etch resistant layer includes an optical thin film layer and an etch-resistant cap layer.
    Type: Grant
    Filed: December 23, 1998
    Date of Patent: August 21, 2001
    Assignee: Aurora Systems, Inc.
    Inventors: Jacob Daniel Haskell, Rong Hsu
  • Patent number: 6252999
    Abstract: A planar wafer based device (e.g., a reflective light valve backplane) includes a substrate having a plurality of surface projections (e.g., pixel mirrors) defining gaps therebetween, an etch-resistant layer formed on the substrate, and a fill layer formed on a portion of the etch-resistant layer in the gaps. In a particular embodiment, the fill layer is a spin-on coating. An optional protective layer formed on the exposed portions of the etch-resistant layer and the fill layer protects the underlying layers during subsequent processing steps.
    Type: Grant
    Filed: December 23, 1998
    Date of Patent: June 26, 2001
    Assignee: Aurora Systems, Inc.
    Inventors: Jacob Daniel Haskell, Rong Hsu
  • Patent number: 6124952
    Abstract: A magnification-variation scanner modifies the resolution merely by changing the object distance and the image distance, with a constant focal distance. The scanner includes a light source, an object lens, an image detector, a holder for carrying the object lens, an optical path delay and a driver. The optical path delay can be located at the midway of the light path from the light source to the object lens, thereby modifying the optical path between the object surface and the object lens. In accompaniment with the movement of the object lens, the dimensions of the image projected over the image detector can be modified. The resolution can therefore be modified. The driver connects between the holder and the optical path delay.
    Type: Grant
    Filed: March 11, 1998
    Date of Patent: September 26, 2000
    Assignee: Acer Peripherals, Inc.
    Inventors: Han-Ping Shieh, Jinn-Chou Yoo, Der-Rong Hsu, Chong-Min Chang
  • Patent number: 5742741
    Abstract: A reconfigurable neural network is disclosed. The neural network includes a plurality of switches each having at least two conductive leads, wherein data flow direction of the conductive leads of the switches is programmed to select one of the conductive leads as input switch lead and select another one of the conductive leads as an output switch lead. A plurality of processing elements each having a plurality of leads connected to the switches, wherein the processing elements and the switches are interconnected in one-dimension manner. Each of the processing elements comprising: (a) a serial-in-parallel-out accumulator having a first input coupled to one of the interconnected switches and generating a first output; (b) an activation function for transforming the first output of the serial-in-parallel-out accumulator and generating a second output; and (c) a parallel-in-serial-out shift register for shifting out the second output of the activation function serially to one of the interconnected switches.
    Type: Grant
    Filed: July 18, 1996
    Date of Patent: April 21, 1998
    Assignee: Industrial Technology Research Institute
    Inventors: Tzi-Dar Chiueh, Hwai-Tsu Chang, Yeh-Rong Hsu, Huang-Lin Yang, Chung-Chih Chang
  • Patent number: D454377
    Type: Grant
    Filed: February 22, 2001
    Date of Patent: March 12, 2002
    Assignees: Hao Yih Trading Co., Ltd., Zenital Inc.
    Inventors: Chen-Rong Hsu, Jenn-Jia Shu
  • Patent number: D301296
    Type: Grant
    Filed: November 21, 1985
    Date of Patent: May 30, 1989
    Inventor: Shin Rong Hsu