Abstract: A multiple-register-access-capable device includes a serial port coupled to a plurality of registers. The multiple-register-access-capable device is controlled by a state machine. Information in one of the registers identifies whether the device is in a single-register or multiple-register mode. The state machine which controls the device operates in a single-register mode if the bit is disabled and operates in a multiple-register mode if the bit is enabled. In single-register mode, the device operates in a manner known in the prior art whereby a single register is identified for reading or writing and data is then either written into the register or read out from the register in response to a write or read request. In multiple register mode, data is written into or read out from all registers in a selected group of registers in the device in response to the write or read request.

Abstract: A multiple-register-access-capable device includes a serial port coupled to a plurality of registers. The multiple-register-access-capable device is controlled by a state machine. Information in one of the registers identifies whether the device is in a single-register or multiple-register mode. The state machine which controls the device operates in a single-register mode if the bit is disabled and operates in a multiple-register mode if the bit is enabled. In single-register mode, the device operates in a manner known in the prior art whereby a single register is identified for reading or writing and data is then either written into the register or read out from the register in response to a write or read request. In multiple register mode, data is written into or read out from all registers in a selected group of registers in the device in response to the write or read request.

Abstract: A multiple-register-access-capable device includes a serial port coupled to a plurality of registers. The multiple-register-access-capable device is controlled by a state machine. Information in one of the registers identifies whether the device is in a single-register or multiple-register mode. The state machine which controls the device operates in a single-register mode if the bit is disabled and operates in a multiple-register mode if the bit is enabled. In single-register mode, the device operates in a manner known in the prior art whereby a single register is identified for reading or writing and data is then either written into the register or read out from the register in response to a write or read request. In multiple register mode, data is written into or read out from all registers in a selected group of registers in the device in response to the write or read request.

Abstract: The invention provides a method and system in which a single pin coupled to an integrated circuit (IC) chip is used to enter configuration information at a power-up time or a reset time (collectively referred to herein as a "reset time" or "reset interval"), and is also used to display output information during normal operation. The pin is coupled to a memory device, so as to store configuration information received during the reset interval. The pin is also coupled to an output driver controlled by a gate which combines output data with a signal indicating reset time, so as to put the output driver into a high impedance state during reset time when the input configuration data is being stored into the device and to drive the pin with the output value during non-reset times. Thus, a user of the IC may cause the memory to receive configuration information from the pin at power-up or during another reset time, while having the pin output normal data at times other than the reset interval.