Patents by Inventor Rong Jiang

Rong Jiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12294337
    Abstract: Methods and devices to implement efficiently an AUX terminal in RF front end receivers using LNAs are described. The described methods implement a smaller number of switches resulting in an overall performance improvement by reducing the noise figure at the input of the LNA. The presented devices can be used in low/high gain and bypass modes and can accommodate an arbitrary number of bands over a wide frequency range.
    Type: Grant
    Filed: March 28, 2023
    Date of Patent: May 6, 2025
    Assignee: PSEMI CORPORATION
    Inventors: Rong Jiang, Khushali Shah
  • Patent number: 12278657
    Abstract: A clamping circuit that may be used to provide efficient and effective voltage clamping in an RF front end. The clamping circuit comprises two series coupled signal path switches and a bypass switch coupled in parallel with the series coupled signal path switches. A diode is coupled from a point between the series coupled signal path switches to a reference potential. In addition, an output selection switch within an RF front end has integrated voltage clamping to more effectively clamp the output voltage from the RF front end. Additional output clamping circuits can be used at various places along a direct gain signal path, along an attenuated gain path and along a bypass path.
    Type: Grant
    Filed: February 23, 2024
    Date of Patent: April 15, 2025
    Assignee: pSemi Corporation
    Inventors: Rong Jiang, Khushali Shah, Peter Bacon
  • Patent number: 12256561
    Abstract: The present application discloses an SiC MOSFET device, including an SiC epitaxial layer in which a trench gate is formed, wherein a first bottom doped region is formed below a bottom surface of a gate trench, a second deep doped region with spacing from the gate trench is formed in the SiC epitaxial layer, the first bottom doped region is connected to a source so that voltage borne by a gate dielectric layer on the bottom surface of the gate trench is determined by gate-source voltage; the second deep doped region extends downward from a top surface of the SiC epitaxial layer, and a bottom surface of the second deep doped region is located below a bottom surface of the first bottom doped region; a top of the second deep doped region is connected to the source. The present application further discloses a method for manufacturing an SiC MOSFET device.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: March 18, 2025
    Assignee: Shenzhen Sanrise-Tech Co., LTD
    Inventors: Dajie Zeng, Rong Jiang
  • Patent number: 12184242
    Abstract: Compact low noise amplifiers that have wide-band coverage while meeting necessary input matching and output matching characteristics. Embodiments include a wide-band, two-stage LNA with minimum degradation in performance compared to multiple narrow-band, single-stage LNAs. A generalized embodiment includes a first amplifier stage having a terminal coupled to a mutually coupled inductor circuit and to a second amplifier stage. The second amplifier stage includes a terminal coupled to the mutually coupled inductor circuit. The mutually coupled inductor circuit comprises electromagnetically coupled inductors L1, L2. Second terminals of the first and second amplifier stages are coupled to respective degeneration inductors. The electromagnetically coupled inductors L1, L2 of the inductor circuit substantially increase the output bandwidth of the LNA with minimum degradation in performance.
    Type: Grant
    Filed: November 6, 2023
    Date of Patent: December 31, 2024
    Assignee: pSemi Corporation
    Inventors: Rong Jiang, Khushali Shah
  • Patent number: 12170708
    Abstract: A data synchronization method and apparatus, applied to a first data service module. The method includes receiving a first request from a second service module, where the first request is used to request to synchronize service data of a first service module; obtaining the service data of the first service module; and sending the service data of the first service module to the second service module. In solutions provided in the present disclosure, the first data service module replaces the first service module to synchronize the service data of the first service module for the second service module.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: December 17, 2024
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Xudong Zhang, Peng Zhang, Rong Jiang, Shenzu Qin
  • Publication number: 20240372513
    Abstract: Methods and devices to support multiple gain states in amplifiers are described. The methods and devices are based on implementing a feedback element in the amplifier and adjusting the impedance of the feedback element to provide a desired gain while maintaining the overall performance of the amplifier and reducing degradation of the S12 parameter. The feedback element includes an adjustable attenuator and a tunable resistive element. The adjustable attenuator is provided in a path that is common to the feedback path and the bypass path of the amplifier. Exemplary implementations of adjustable attenuators are also presented.
    Type: Application
    Filed: July 12, 2024
    Publication date: November 7, 2024
    Inventors: Rong JIANG, Parvez DARUWALLA, Khushali SHAH
  • Publication number: 20240283407
    Abstract: Methods and devices for amplifying an input RF signal according to at least two gain-states is described. According to one aspect, a multi gain amplifier circuit including a low noise amplifier having a stack of transistors is used for amplification of the input RF signal. When switching from a low gain-state to a high gain-state, the drain-to-source voltage of the output transistor of the stack is increased to affect region of operation of the output transistor, and thereby reduce non-linearity at the output of the amplifier. When switching from the high gain-state to the low gain-state, the drain-to-source voltage of the input transistor of the stack is increased to affect region of operation of the input transistor, and thereby reduce non-linearity at the output of the amplifier.
    Type: Application
    Filed: January 30, 2024
    Publication date: August 22, 2024
    Inventors: Rong Jiang, Haopei Deng
  • Publication number: 20240275416
    Abstract: A clamping circuit that may be used to provide efficient and effective voltage clamping in an RF front end. The clamping circuit comprises two series coupled signal path switches and a bypass switch coupled in parallel with the series coupled signal path switches. A diode is coupled from a point between the series coupled signal path switches to a reference potential. In addition, an output selection switch within an RF front end has integrated voltage clamping to more effectively clamp the output voltage from the RF front end. Additional output clamping circuits can be used at various places along a direct gain signal path, along an attenuated gain path and along a bypass path.
    Type: Application
    Filed: February 23, 2024
    Publication date: August 15, 2024
    Inventors: Rong Jiang, Khushali Shah, Peter Bacon
  • Patent number: 12063016
    Abstract: Methods and devices to support multiple gain states in amplifiers are described. The methods and devices are based on implementing a feedback element in the amplifier and adjusting the impedance of the feedback element to provide a desired gain while maintaining the overall performance of the amplifier and reducing degradation of the S12 parameter. The feedback element includes an adjustable attenuator and a tunable resistive element. The adjustable attenuator is provided in a path that is common to the feedback path and the bypass path of the amplifier. Exemplary implementations of adjustable attenuators are also presented.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: August 13, 2024
    Assignee: pSemi Corporation
    Inventors: Rong Jiang, Parvez Daruwalla, Khushali Shah
  • Publication number: 20240254361
    Abstract: A method of preparing a high performance low isocyanate polyurethane top coating effective to protect external architectural surfaces and substantially minimizing applicator exposure to isocyanates, including: providing an amount of compound A chosen from a fluoroethylene vinyl ether (FEVE) moiety of formula (I); providing an amount of Compound B chosen from a silane functional isocyanate of general formula (II); where compound A and compound B are present in a stoichiometric ratio of 1:1; providing an effective amount of a catalyst of compound C; introducing compounds A and B into a reaction vessel and stirring the compounds in an inert atmosphere at a predetermined temperature and a predetermined time; where the resultant silane functional FEVE resin is substantially free of unreacted isocyanate.
    Type: Application
    Filed: August 16, 2022
    Publication date: August 1, 2024
    Applicant: A & I Coatings Group Pty Ltd
    Inventors: Fu Rong JIANG, Stephen BAILEY
  • Publication number: 20240250702
    Abstract: Methods and devices to support multiple frequency bands in radio frequency (RF) circuits are shown. The described methods and devices are based on adjusting the effective width of a transistor in such circuits by selectively disposing matching transistors in parallel with the transistor. The presented devices and methods can be used in RF circuits including low noise amplifiers (LNAs), RF receiver front-ends or any other RF circuits where input matching to wideband inputs is required.
    Type: Application
    Filed: April 3, 2024
    Publication date: July 25, 2024
    Inventors: Parvez DARUWALLA, Rong JIANG, Sung Kyu HAN, Khushali SHAH
  • Patent number: 12040962
    Abstract: In a routing information management method, a primary route generation unit generates routing information related to a TCP packet, and the primary route generation unit sends the routing information and first identification information of the routing information to a database unit, where the first identification information is determined based on the TCP packet.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: July 16, 2024
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Haijun Xu, Xudong Zhang, Rong Jiang, Feng Guo, Yi Xiong
  • Publication number: 20240213932
    Abstract: New multi-input LNA architectures with improved passive mode negative gain performance that reconfigure the bypass path routes to achieve wide-band bypass matching and make bypass matching for lower frequency bands possible to achieve desired gain specifications. In a first embodiment, improved wide-band performance is provided by a bypass path that optionally does not pass through an impedance matching network and thus has a dedicated path to RFOUT. In a second embodiment, improved wide-band performance is provided by a bypass path that does not pass through an input inductor. In a third embodiment, improved wide-band performance is provided by a bypass path that has a first portion that optionally does not pass through an impedance matching network, and a second portion that does not pass through an input inductor. In a fourth embodiment, improved wide-band performance is provided by selectively disabling a load inductor in some modes of operation.
    Type: Application
    Filed: December 22, 2022
    Publication date: June 27, 2024
    Inventors: Rong Jiang, Sung Kyu Han, Parvez H. Daruwalla, Khushali Shah
  • Publication number: 20240136984
    Abstract: Compact low noise amplifiers that have wide-band coverage while meeting necessary input matching and output matching characteristics. Embodiments include a wide-band, two-stage LNA with minimum degradation in performance compared to multiple narrow-band, single-stage LNAs. A generalized embodiment includes a first amplifier stage having a terminal coupled to a mutually coupled inductor circuit and to a second amplifier stage. The second amplifier stage includes a terminal coupled to the mutually coupled inductor circuit. The mutually coupled inductor circuit comprises electromagnetically coupled inductors L1, L2. Second terminals of the first and second amplifier stages are coupled to respective degeneration inductors. The electromagnetically coupled inductors L1, L2 of the inductor circuit substantially increase the output bandwidth of the LNA with minimum degradation in performance.
    Type: Application
    Filed: November 6, 2023
    Publication date: April 25, 2024
    Inventors: Rong Jiang, Khushali Shah
  • Publication number: 20240126948
    Abstract: A numerical simulation optimization method of impact damage based on a laser mapped solid mesh is provided, including: measuring an impact damage size, a damage profile, a surface residual strain and a surface residual stress of a solid mesh element around the damage after firing a bullet by a light gas gun to impact a mesh area of a sample and obtaining the impact damage; establishing a parameterized impact finite element model to obtain a numerically simulated impact damage size, a numerically simulated impact damage profile, a numerically simulated surface residual strain and the surface residual stress of the surface solid mesh element; and calculating relative errors between the experimental measurements and the numerically simulated impact damage size, damage profile, surface residual strain and residual stress; and determining whether the relative errors are all less than expected values until a numerical simulation result meeting the accuracy requirements are obtained.
    Type: Application
    Filed: December 29, 2022
    Publication date: April 18, 2024
    Applicant: NANJING UNIVERSITY OF AERONAUTICS AND ASTRONAUTICS
    Inventors: Xu JIA, Yingdong SONG, Rong JIANG, Dawei WANG
  • Publication number: 20240125128
    Abstract: This invention discloses digitally printed plate, the manufacturing method and applications thereof, is characterized in that the digitally printed plate is of respectively from top to bottom surface lacquer layer, texture layer, second wear layer, first wear layer, pattern layer, bottom lacquer layer, base layer. The digitally printed plated has various patterns, with sufficient materials, printing unrepeatable stereoscopic pattern is possible, so it can satisfy customers' personalized customization requirements, without wasting abundant time or cost, and with process reduced, production efficiency is improved, enabling order manufacturing order insert and sample making at any time.
    Type: Application
    Filed: March 24, 2021
    Publication date: April 18, 2024
    Inventors: Jun Yuan, Quanshan Cheng, Juan Chen, Haiqing Qian, Rong Jiang, Yuan Liu
  • Patent number: 11923883
    Abstract: A clamping circuit that may be used to provide efficient and effective voltage clamping in an RF front end. The clamping circuit comprises two series coupled signal path switches and a bypass switch coupled in parallel with the series coupled signal path switches. A diode is coupled from a point between the series coupled signal path switches to a reference potential. In addition, an output selection switch within an RF front end has integrated voltage clamping to more effectively clamp the output voltage from the RF front end. Additional output clamping circuits can be used at various places along a direct gain signal path, along an attenuated gain path and along a bypass path.
    Type: Grant
    Filed: January 25, 2023
    Date of Patent: March 5, 2024
    Assignee: pSemi Corporation
    Inventors: Rong Jiang, Khushali Shah, Peter Bacon
  • Patent number: 11894809
    Abstract: Methods and devices for amplifying an input RF signal according to at least two gain-states is described. According to one aspect, a multi gain amplifier circuit including a low noise amplifier having a stack of transistors is used for amplification of the input RF signal. When switching from a low gain-state to a high gain-state, the drain-to-source voltage of the output transistor of the stack is increased to affect region of operation of the output transistor, and thereby reduce non-linearity at the output of the amplifier. When switching from the high gain-state to the low gain-state, the drain-to-source voltage of the input transistor of the stack is increased to affect region of operation of the input transistor, and thereby reduce non-linearity at the output of the amplifier.
    Type: Grant
    Filed: May 5, 2022
    Date of Patent: February 6, 2024
    Assignee: pSemi Corporation
    Inventors: Rong Jiang, Haopei Deng
  • Publication number: 20230387863
    Abstract: Feedback methods and devices to reduce gain in RF amplifiers, more in particular LNAs, are disclosed. The described methods are based on providing feedback paths from the drain terminal of one of the LNA cascode transistors to the source terminal of the LNA input transistor, or from the gate terminal of the input transistor to the source terminal of the LNA input transistor. The disclosed methods can be combined with one another or with existing feedback methods to provide further flexibility and improved tradeoffs when designing LNAs for applications having different requirements.
    Type: Application
    Filed: May 27, 2022
    Publication date: November 30, 2023
    Inventors: Parvez DARUWALLA, Rong JIANG, Khushali SHAH
  • Patent number: 11817830
    Abstract: Compact low noise amplifiers that have wide-band coverage while meeting necessary input matching and output matching characteristics. Embodiments include a wide-band, two-stage LNA with minimum degradation in performance compared to multiple narrow-band, single-stage LNAs. A generalized embodiment includes a first amplifier stage having a terminal coupled to a mutually coupled inductor circuit and to a second amplifier stage. The second amplifier stage includes a terminal coupled to the mutually coupled inductor circuit. The mutually coupled inductor circuit comprises electromagnetically coupled inductors L1, L2. Second terminals of the first and second amplifier stages are coupled to respective degeneration inductors. The electromagnetically coupled inductors L1, L2 of the inductor circuit substantially increase the output bandwidth of the LNA with minimum degradation in performance.
    Type: Grant
    Filed: May 24, 2022
    Date of Patent: November 14, 2023
    Assignee: pSemi Corporation
    Inventors: Rong Jiang, Khushali Shah