Patents by Inventor Rong Liang

Rong Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210391677
    Abstract: A connector is disclosed. In an embodiment, the connector includes a first connection part and a second connection part. The first connection part and the second connection part form a groove suitable for accommodating a circuit board when the first connection part and the second connection part are assembled together, and elastic parts are disposed on opposite inner surfaces of the groove. Furthermore, a corresponding three-way transmission and conversion circuit module is disclosed, including the connector.
    Type: Application
    Filed: October 23, 2018
    Publication date: December 16, 2021
    Applicant: Siemens Aktiengesellschaft
    Inventors: Rong Liang MU, Hai Jun WANG, Bin YANG
  • Patent number: 9760112
    Abstract: A semiconductor chip comprising: an internal clock circuit for generating an internal clock signal; a first phase shift device for shifting the phase of an external clock signal and outputting a phase shifting clock signal; a multiplexer, for selectively outputting one of the internal clock signal and the phase shifting clock signal to be a first clock signal; a second phase shift device, for shifting the phase of the first clock signal and outputting a second clock signal; an first output pad, for outputting the first clock signal; and a controllable pad. The controllable pad is controlled to selectively act as an input pad for receiving the external signal and transmitting the external clock signal to the first phase shift device, or act as a second output pad for transmitting the second clock signal.
    Type: Grant
    Filed: July 3, 2015
    Date of Patent: September 12, 2017
    Assignee: MEDIATEK INC.
    Inventors: Ming-Luen Liou, Rong-Liang Chiou
  • Publication number: 20160132976
    Abstract: A bilateral service app for wine tracking and management includes, structurally, a service function device, which enables a sales side to track and manage information related to a user side, a linking device, which allows the user side to the wine information storage device to inquire information related to the wine, a data recording module, which records drinking condition of the user side in respect of the wine, and a user feedback module, which allows the user side to provide comments regarding the wine. With the above structure, the user side, before purchasing a bottle of wine, may connect, via the linking device, to the wine information storage device to inquire information related to the wine and may record the drinking condition of the wine in the data recording module and provide comments of the wine in the user feedback module.
    Type: Application
    Filed: November 12, 2014
    Publication date: May 12, 2016
    Inventor: Hsien-Rong Liang
  • Publication number: 20150301556
    Abstract: A semiconductor chip comprising: an internal clock circuit for generating an internal clock signal; a first phase shift device for shifting the phase of an external clock signal and outputting a phase shifting clock signal; a multiplexer, for selectively outputting one of the internal clock signal and the phase shifting clock signal to be a first clock signal; a second phase shift device, for shifting the phase of the first clock signal and outputting a second clock signal; an first output pad, for outputting the first clock signal; and a controllable pad. The controllable pad is controlled to selectively act as an input pad for receiving the external signal and transmitting the external clock signal to the first phase shift device, or act as a second output pad for transmitting the second clock signal.
    Type: Application
    Filed: July 3, 2015
    Publication date: October 22, 2015
    Inventors: Ming-Luen Liou, Rong-Liang Chiou
  • Patent number: 9106329
    Abstract: A semiconductor chip comprises an internal clock circuit, a first phase shift device, a second phase shift device, a multiplexer, a first output pad, and a controllable pad. The internal clock circuit generates an internal clock signal. The first phase shift device shifts the phase of an external clock signal and outputs a phase shifting clock signal. The multiplexer selectively outputs one of the internal clock signal and the phase shifting clock signal to be a first clock signal. The second phase shift device shifts the phase of the first clock signal and outputs a second clock signal. The first output pad outputs the first clock signal. The controllable pad is controlled to selectively act as an input pad for receiving the external signal, or act as a second output pad for transmitting the second clock signal.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: August 11, 2015
    Assignee: MEDIATEK INC.
    Inventors: Ming-Luen Liou, Rong-Liang Chiou
  • Patent number: 8910233
    Abstract: A signal processing apparatus includes a first signal processing block and a second signal processing block. The first signal processing block is utilized for processing an input signal to generate a first target processing result, including a plurality of packets initially reproduced from the input signal, to an output port of the first signal processing circuit, where each of the packets contains a corresponding packet identifier (PID). The second signal processing block has an input port coupled to the output port of the first signal processing circuit, and is utilized for processing the first target processing result according to PIDs of the packets and accordingly generating a second target processing result. There is no buffer coupled between the output port of the first signal processing circuit and the input port of the second signal processing circuit.
    Type: Grant
    Filed: November 20, 2009
    Date of Patent: December 9, 2014
    Assignee: Mediatek Inc.
    Inventors: Ching-Chieh Wang, You-Min Yeh, Chin-Wang Yeh, Rong-Liang Chiou
  • Patent number: 8902893
    Abstract: A packet processing apparatus includes a packet identifying unit and a packet modifying unit. The packet identifying unit is utilized for receiving a plurality of packets and checking identification information and data length information which are derived from the received packets to identify first packets from the received packets. The packet modifying unit is coupled to the packet identifying unit, and is utilized for checking payloads of the first packets to identify second packets from the first packets, where each of the second packets has specific data included in a payload thereof, and for modifying at least the payload of each of the second packets.
    Type: Grant
    Filed: December 8, 2009
    Date of Patent: December 2, 2014
    Assignee: Mediatek Inc.
    Inventors: Chin-Wang Yeh, You-Min Yeh, Rong-Liang Chiou, Yu-Hsiung Deng, Ching-Chieh Wang
  • Publication number: 20130044738
    Abstract: A photo kiosk wireless transmission system includes a mobile device and a data processing device. The mobile device includes an application program embedded therein and the data processing device includes a corresponding application program, so that transmission of multimedia data can be carried out between the mobile device and the data processing device through the corresponding application programs. To carry out the transmission, a Wi-Fi transmission device included in the mobile device and a Wi-Fi reception device included in the data processing device must be activated. As such, the multimedia data contained in the mobile device can be transmitted to the data processing device to allow the data processing device to carry out processing of the multimedia data (such as printing, storage, or uploading through the Internet to a community interaction platform), thereby improving convenience of use through changing the process and path of the known technology of multimedia data uploading.
    Type: Application
    Filed: August 15, 2011
    Publication date: February 21, 2013
    Inventor: HSIEN-RONG LIANG
  • Patent number: 8321767
    Abstract: A packet processing apparatus includes a packet identifying unit and a packet modifying unit. The packet identifying unit is utilized for receiving a plurality of packets and checking identification information derived from the received packets to identify first packets from the received packets. The packet modifying unit is coupled to the packet identifying unit, and is utilized for checking payloads of the first packets to identify second packets from the first packets, where each of the second packets has specific data included in a payload thereof, and for modifying at least the payload of each of the second packets.
    Type: Grant
    Filed: November 24, 2009
    Date of Patent: November 27, 2012
    Assignee: Mediatek Inc.
    Inventors: Chin-Wang Yeh, You-Min Yeh, Rong-Liang Chiou, Yu-Hsiung Deng, Ching-Chieh Wang
  • Patent number: 8286051
    Abstract: A digital communication device is provided for decoding a data stream to generate a receiver output. In the digital communication device, a burst error detector determines burst noise locations corresponding to the data stream according to an error-check equation and accordingly generates a burst error indicator. Thereafter, an inner decoder decodes the data stream to generate an inner decoded stream, comprising an erasure marker for performing an erasure marking process on the inner decoded stream based on the burst error indicator to generate an erasure indicator corresponding to the inner decoded stream. An outer decoder then decodes the inner decoded stream with reference to the erasure indicator to generate the receiver output.
    Type: Grant
    Filed: September 8, 2008
    Date of Patent: October 9, 2012
    Assignee: Mediatek Inc.
    Inventors: Rong-Liang Chiou, Ming-Luen Liou
  • Publication number: 20120194234
    Abstract: A semiconductor chip comprises an internal clock circuit, a first phase shift device, a second phase shift device, a multiplexer, a first output pad, and a controllable pad. The internal clock circuit generates an internal clock signal. The first phase shift device shifts the phase of an external clock signal and outputs a phase shifting clock signal. The multiplexer selectively outputs one of the internal clock signal and the phase shifting clock signal to be a first clock signal. The second phase shift device shifts the phase of the first clock signal and outputs a second clock signal. The first output pad outputs the first clock signal. The controllable pad is controlled to selectively act as an input pad for receiving the external signal, or act as a second output pad for transmitting the second clock signal.
    Type: Application
    Filed: January 12, 2012
    Publication date: August 2, 2012
    Inventors: Ming-Luen Liou, Rong-Liang Chiou
  • Patent number: 8209583
    Abstract: An apparatus for error-correcting an input signal to generate an output signal. The apparatus includes an unreliable-location determining module for determining unreliable-locations of the input signal and generating an indication signal accordingly, a first error-correcting module for error-correcting the input signal to generate a first candidate signal, a second error-correcting module coupled to the unreliable-location determining module for error-correcting the input signal with reference to the indication signal to generate a second candidate signal, and a selecting module coupled to the first and second error-correcting modules for selecting one of the first and second candidate signals to be the output signal.
    Type: Grant
    Filed: January 13, 2010
    Date of Patent: June 26, 2012
    Assignee: Mediatek Inc.
    Inventor: Rong-Liang Chiou
  • Patent number: 8202681
    Abstract: A hybrid mask set for exposing a plurality of layers on a semiconductor substrate to create an integrated circuit device is disclosed. The hybrid mask set includes a first group of one or more multi-layer masks (MLMs) for a first subset of the plurality of layers. Each MLM includes a plurality of different images for different layers, the images being separated by a relatively wide image spacer. The hybrid mask set also includes a first group of one or more production-ready masks for a second subset of the plurality of layers. Each production-ready mask includes a plurality of similar images for a common layer, each image being separated by a relatively narrow scribe street.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: June 19, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Feng-Lung Lin, Kuan-Liang Wu, Che-Rong Liang, Fei-Gwo Tsai
  • Patent number: 8103037
    Abstract: A system for producing parameters for a bass-enhanced loudspeaker enclosure; meanwhile, a low-frequency extended frequency, a quality and quantity ratio and radius of a port need to be defined for the system. Also, the resonance frequency of a mechanical system and the quality and quantity of a mechanical system are fixed to obtain the parameters for the frequency ratio, the length of the duct and the cavity volume inside the device, etc. and to manufacture the bass-enhanced loudspeaker enclosure.
    Type: Grant
    Filed: February 21, 2008
    Date of Patent: January 24, 2012
    Assignee: National Chiao Tung University
    Inventors: Ming-Sian R. Bai, Huan-Sheng Zhang, Rong-Liang Chen
  • Publication number: 20110281208
    Abstract: A hybrid mask set for exposing a plurality of layers on a semiconductor substrate to create an integrated circuit device is disclosed. The hybrid mask set includes a first group of one or more multi-layer masks (MLMs) for a first subset of the plurality of layers. Each MLM includes a plurality of different images for different layers, the images being separated by a relatively wide image spacer. The hybrid mask set also includes a first group of one or more production-ready masks for a second subset of the plurality of layers. Each production-ready mask includes a plurality of similar images for a common layer, each image being separated by a relatively narrow scribe street.
    Type: Application
    Filed: July 21, 2011
    Publication date: November 17, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Feng-Lung Lin, Kuan-Liang Wu, Fei-Gwo Tsai, Che-Rong Liang
  • Patent number: 8054983
    Abstract: The present invention discloses a method for parameter identification and parameter optimization of microspeakers. Measurement procedures for identifying electromechanical constants of microspeaker and a GUI are developed to facilitate estimation of electroacoustic parameters of the microspeaker under test. In light of the thus identified microspeaker parameters, a parameter optimization procedure is carried out to obtain the design that attains the best acoustic performance with minimum harmonic distortion.
    Type: Grant
    Filed: July 27, 2006
    Date of Patent: November 8, 2011
    Assignee: National Chiao Tung University
    Inventors: Mingsian R. Bai, Rong Liang Chen
  • Patent number: 8007576
    Abstract: A chrome-free corrosion inhibitor composition includes: titanium chloride; a stabilizer including a mixture of hydrogen peroxide and at least a compound selected from nitric acid, persulfate, nitrate, and chlorate; and a film-forming enhancer selected from monosaccharide, oligosaccharide, polysaccharide, derivatives of saccharide, and combinations thereof.
    Type: Grant
    Filed: May 22, 2008
    Date of Patent: August 30, 2011
    Assignee: Ya Thai Chemical Co., Ltd.
    Inventors: Jyh-Rong Liang, Po-Ya Hsu, Ming-Chuan Wang, Chia-Chih Ou, Wen-Chieh Lin, I-Lin Cheng
  • Patent number: 8007966
    Abstract: A method of fabricating a mask set is provided. The method includes providing mask data associated with a plurality of mask layers. The mask data includes a first pattern associated with a first technology node and a second pattern associated with a second technology node. The method continues with determining to form a multi-technology node mask (MTM) for a first mask layer of the plurality of mask layers. The MTM for the first mask layer is formed, which includes features associated with the first pattern and features associated with the second pattern.
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: August 30, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Feng Lung Lin, Kuan Liang Wu, Fei-Gwo Tsai, Che-Rong Liang
  • Patent number: 8003281
    Abstract: A hybrid mask set for exposing a plurality of layers on a semiconductor substrate to create an integrated circuit device is disclosed. The hybrid mask set includes a first group of one or more multi-layer masks (MLMs) for a first subset of the plurality of layers. Each MLM includes a plurality of different images for different layers, the images being separated by a relatively wide image spacer. The hybrid mask set also includes a first group of one or more production-ready masks for a second subset of the plurality of layers. Each production-ready mask includes a plurality of similar images for a common layer, each image being separated by a relatively narrow scribe street.
    Type: Grant
    Filed: October 13, 2008
    Date of Patent: August 23, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd
    Inventors: Feng-Lung Lin, Kuan-Liang Wu, Che-Rong Liang, Fei-Gwo Tsai
  • Patent number: D928086
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: August 17, 2021
    Assignee: Siemens Aktiengesellschaft
    Inventors: Rong Liang Mu, Hai Jun Wang, Guan Yong Yu