Patents by Inventor Rong Xuan

Rong Xuan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220206578
    Abstract: A method for generating a haptic feedback can be applied to a terminal, and include: in response to an interface element on a display interface of the terminal being touched, determining a first interface element type corresponding to the interface element, and determining a first haptic effect corresponding to the first interface element type based on a matchup between interface element types and haptic effects, where different interface element types correspond to different haptic effects; generating a haptic feedback of the first haptic effect.
    Type: Application
    Filed: May 31, 2021
    Publication date: June 30, 2022
    Applicant: BEIJING XIAOMI MOBILE SOFTWARE CO., LTD.
    Inventors: Zhe LIANG, Qiaozhuo CHEN, Huiying YANG, Fan JIN, Wenwen LI, Yuefeng MA, Yixin ZHAO, Rong LIU, Liang XUAN, Qing LIU
  • Patent number: 9397281
    Abstract: A carrier for carrying a semiconductor layer having a growth surface and at least one nano-patterned structure on the growth surface is provided. The at least one nano-patterned structure on the growth surface of the carrier has a plurality of mesas, a recess is formed between two adjacent mesas, in which a depth of the recess ranges from 10 nm to 500 nm, and a dimension of the mesa ranges from 10 nm to 800 nm.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: July 19, 2016
    Assignee: Industrial Technology Research Institute
    Inventors: Yi-Keng Fu, Rong Xuan, Hsun-Chih Liu
  • Patent number: 9159788
    Abstract: A nitride semiconductor structure including a silicon substrate, a nucleation layer, a buffer layer and a nitride semiconductor layer is provided. The nucleation layer is disposed on the silicon substrate. The buffer layer is disposed on the nucleation layer, in which the buffer layer includes n sub-buffer layers where n?2, and each of the sub-buffer layers has island structures. The nitride semiconductor layer is disposed on the buffer layer.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: October 13, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Chih-Wei Hu, Chen-Zi Liao, Hsun-Chih Liu, Rong Xuan
  • Patent number: 9112077
    Abstract: A semiconductor structure including a silicon substrate, a nucleation layer and a plurality of multi-layer sets is provided. The nucleation layer is disposed on the silicon substrate. The multi-layer sets are stacked over the nucleation layer, and each of the multi-layer sets includes a plurality of first sub-layers and a plurality of second sub-layers stacked alternately. A material of the first sub-layers and the second sub-layers includes Al-containing III-V group compound, wherein an average content of aluminum of the multi-layer sets decreases as a minimum distance between each of the multi-layer sets and the silicon substrate increases, and an aluminum content of the first sub-layers is different from an aluminum content of the second sub-layers.
    Type: Grant
    Filed: April 28, 2014
    Date of Patent: August 18, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Chen-Zi Liao, Chih-Wei Hu, Hsun-Chih Liu, Yen-Hsiang Fang, Rong Xuan
  • Patent number: 9111851
    Abstract: Provided is an enhancement mode GaN-based transistor device including an epitaxial stacked layer disposed on a substrate; a source layer and a drain layer disposed on a surface of the epitaxial stacked layer; a p-type metal oxide layer disposed between the source layer and the drain layer; and a gate layer disposed on the p-type metal oxide layer. Besides, the p-type metal oxide layer includes a body part disposed on the surface of the epitaxial stacked layer, and a plurality of extension parts connecting the body part and extending into the epitaxial stacked layer. With such structure, the enhancement mode GaN-based transistor device can effectively suppress generation of the gate leakage current.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: August 18, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Wei-Hung Kuo, Suh-Fang Lin, Rong Xuan
  • Publication number: 20150187876
    Abstract: A nitride semiconductor structure including a silicon substrate, a nucleation layer, a buffer layer and a nitride semiconductor layer is provided. The nucleation layer is disposed on the silicon substrate. The buffer layer is disposed on the nucleation layer, in which the buffer layer includes n sub-buffer layers where n?2, and each of the sub-buffer layers has island structures. The nitride semiconductor layer is disposed on the buffer layer.
    Type: Application
    Filed: December 31, 2013
    Publication date: July 2, 2015
    Applicant: Industrial Technology Research Institute
    Inventors: Chih-Wei Hu, Chen-Zi Liao, Hsun-Chih Liu, Rong Xuan
  • Publication number: 20150179880
    Abstract: A nitride light emitting diode structure including a first type doped semiconductor layer, a second type doped semiconductor layer, a light emitting layer, a first metal pad, a second metal pad and a magnetic film is disclosed. The magnetic film disposed between the first metal pad and the first type doped semiconductor layer includes a zinc oxide (ZnO) layer doped with cobalt (Co). The content of Co in the ZnO layer ranges from 5% to 25% by molar ratio.
    Type: Application
    Filed: December 24, 2013
    Publication date: June 25, 2015
    Applicant: Industrial Technology Research Institute
    Inventors: Yen-Hsiang Fang, Rong Xuan, Chia-Lung Tsai, Yu-Hsiang Chang
  • Publication number: 20150137332
    Abstract: A carrier for carrying a semiconductor layer having a growth surface and at least one nano-patterned structure on the growth surface is provided. The at least one nano-patterned structure on the growth surface of the carrier has a plurality of mesas, a recess is formed between two adjacent mesas, in which a depth of the recess ranges from 10 nm to 500 nm, and a dimension of the mesa ranges from 10 nm to 800 nm.
    Type: Application
    Filed: December 29, 2014
    Publication date: May 21, 2015
    Inventors: Yi-Keng Fu, Rong Xuan, Hsun-Chih Liu
  • Patent number: 8952411
    Abstract: A light emitting diode device may include a carrier, a p-type and n-type semiconductor layers, an active layer, a first electrode and a second electrode is provided. The carrier has a growth surface and at least one nano-patterned structure on the growth surface, in which the carrier includes a substrate and a semiconductor capping layer disposed between the substrate and the n-type semiconductor layer. The n-type semiconductor layer and the p-type semiconductor layer are located over the growth surface of the carrier. The active layer is located between the n-type and p-type semiconductor layers, in which a wavelength ? of light emitted by the active layer is 222 nm???405 nm, and a defect density of the active layer is less than or equal to 5×1010/cm2. The first and second electrodes are respectively connected to the n-type and p-type semiconductor layers. A carrier for carrying a semiconductor layer is also provided.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: February 10, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Yi-Keng Fu, Rong Xuan, Hsun-Chih Liu
  • Patent number: 8946775
    Abstract: A nitride semiconductor structure is provided. The nitride semiconductor structure at least includes a silicon substrate, a AlN layer, a AlGaN layer and a GaN layer formed on the AlGaN layer. The silicon substrate has a surface tilted at 0<tilted?0.5° with respect to a axis perpendicular to a (111) crystal plane, and the AlN layer is formed on the surface. The AlGaN layer is formed on the AlN layer. Moreover, an Al content in the AlGaN layer is decreased gradually in a layer thickness direction from the silicon substrate side toward the GaN layer side.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: February 3, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Chen-Zi Liao, Chih-Wei Hu, Yen-Hsiang Fang, Rong Xuan
  • Patent number: 8779468
    Abstract: A nitride semiconductor structure including a silicon substrate, a nucleation layer, a discontinuous defect blocking layer, a buffer layer and a nitride semiconductor layer is provided. The nucleation layer disposed on the silicon substrate, wherein the nucleation layer has a defect density d1. A portion of the nucleation layer is covered by the discontinuous defect blocking layer. The buffer layer is disposed on the discontinuous defect blocking layer and a portion of the nucleation layer that is not covered by the discontinuous defect blocking layer. The nitride semiconductor layer is disposed on the buffer layer. A ratio of a defect density d2 of the nitride semiconductor layer to the defect density d1 of the nucleation layer is less than or equal to about 0.5, at a location where about 1 micrometer above the interface between the nitride semiconductor layer and the buffer layer.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: July 15, 2014
    Assignee: Industrial Technology Research Institute
    Inventors: Yen-Hsiang Fang, Chien-Pin Lu, Chen-Zi Liao, Rong Xuan, Yi-Keng Fu, Chih-Wei Hu, Hsun-Chih Liu
  • Publication number: 20140131732
    Abstract: A light emitting diode device may include a carrier, a p-type and n-type semiconductor layers, an active layer, a first electrode and a second electrode is provided. The carrier has a growth surface and at least one nano-patterned structure on the growth surface, in which the carrier includes a substrate and a semiconductor capping layer disposed between the substrate and the n-type semiconductor layer. The n-type semiconductor layer and the p-type semiconductor layer are located over the growth surface of the carrier. The active layer is located between the n-type and p-type semiconductor layers, in which a wavelength ? of light emitted by the active layer is 222 nm???405 nm, and a defect density of the active layer is less than or equal to 5×1010/cm2. The first and second electrodes are respectively connected to the n-type and p-type semiconductor layers. A carrier for carrying a semiconductor layer is also provided.
    Type: Application
    Filed: November 15, 2013
    Publication date: May 15, 2014
    Applicant: Industrial Technology Research Institute
    Inventors: Yi-Keng Fu, Rong Xuan, Hsun-Chih Liu
  • Publication number: 20140124833
    Abstract: A nitride semiconductor structure including a silicon substrate, a nucleation layer, a discontinuous defect blocking layer, a buffer layer and a nitride semiconductor layer is provided. The nucleation layer disposed on the silicon substrate, wherein the nucleation layer has a defect density d1. A portion of the nucleation layer is covered by the discontinuous defect blocking layer. The buffer layer is disposed on the discontinuous defect blocking layer and a portion of the nucleation layer that is not covered by the discontinuous defect blocking layer. The nitride semiconductor layer is disposed on the buffer layer. A ratio of a defect density d2 of the nitride semiconductor layer to the defect density d1 of the nucleation layer is less than or equal to about 0.5, at a location where about 1 micrometer above the interface between the nitride semiconductor layer and the buffer layer.
    Type: Application
    Filed: December 26, 2012
    Publication date: May 8, 2014
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yen-Hsiang Fang, Chien-Pin Lu, Chen-Zi Liao, Rong Xuan, Yi-Keng Fu, Chih-Wei Hu, Hsun-Chih Liu
  • Publication number: 20140103354
    Abstract: A nitride semiconductor structure including a silicon substrate, a nucleation layer, a buffer layer and a nitride semiconductor layer is provided. The nucleation layer disposed on the silicon substrate includes a cubic silicon carbon nitride (SiCN) layer. The buffer layer is disposed on the nucleation layer. The nitride semiconductor layer is disposed on the buffer layer.
    Type: Application
    Filed: October 9, 2013
    Publication date: April 17, 2014
    Applicant: Industrial Technology Research Institute
    Inventors: Chih-Wei Hu, Chen-Zi Liao, Yen-Hsiang Fang, Rong Xuan
  • Patent number: 8698166
    Abstract: A light emitting chip package module includes a substrate, a light emitting chip package structure, and a magnetic device. The substrate has a surface. The light emitting chip package structure is disposed on the surface of the substrate. The light emitting chip package structure includes a carrier, a light emitting chip, and a sealant. The light emitting chip is disposed on and electrically connected to the carrier. The sealant is disposed on the carrier and covers the light emitting chip. The magnetic device is disposed next to the light emitting chip package structure to apply a magnetic field to the light emitting chip.
    Type: Grant
    Filed: July 16, 2010
    Date of Patent: April 15, 2014
    Assignee: Industrial Technology Research Institute
    Inventors: Hsueh-Chih Chang, Rong Xuan, Chao-Wei Li, Chih-Hao Hsu
  • Publication number: 20140097443
    Abstract: A nitride semiconductor device includes a silicon substrate, a nucleation layer, a buffer layer, a first type nitride semiconductor stacked layer, a light-emitting layer and a second type nitride semiconductor layer. The nucleation layer is disposed on the silicon substrate. The buffer layer is disposed on the nucleation layer. The first type nitride semiconductor stacked layer is disposed on the buffer layer. The first type nitride semiconductor stacked layer being a plurality of lattice mismatch stacked layers includes a plurality of first nitride semiconductor layers and a plurality of second nitride semiconductor layers. The first nitride semiconductor layers and the second nitride semiconductor layers are stacked alternately, and the first nitride semiconductor layers and the second nitride semiconductor layers are different material. The light-emitting layer is disposed on the first type nitride semiconductor stacked layer.
    Type: Application
    Filed: October 9, 2012
    Publication date: April 10, 2014
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yen-Hsiang Fang, Rong Xuan, Chen-Zi Liao, Yi-Keng Fu, Chih-Wei Hu, Chien-Pin Lu, Hsun-Chih Liu
  • Publication number: 20140097444
    Abstract: A nitride semiconductor device includes a silicon substrate, a nucleation layer, a buffer layer, a first type nitride semiconductor layer, a light-emitting layer and a second type nitride semiconductor layer is provided. The nucleation layer is disposed on the silicon substrate. The buffer layer is disposed on the nucleation layer. The first type nitride semiconductor layer is disposed on the buffer layer. The first type nitride semiconductor layer is doped with a first type dopant, at least one of the buffer layer and the first type nitride semiconductor layer comprises a codopant distributed therein, and an atomic radius of the codopant is larger than an atomic radius of the first type dopant. The light-emitting layer is disposed on the first type nitride semiconductor layer. The second type nitride semiconductor layer is disposed on the light-emitting layer, the second type nitride semiconductor layer comprising a second type dopant.
    Type: Application
    Filed: October 9, 2012
    Publication date: April 10, 2014
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yen-Hsiang Fang, Chen-Zi Liao, Rong Xuan, Chien-Pin Lu, Yi-Keng Fu, Chih-Wei Hu, Hsun-Chih Liu
  • Publication number: 20140097442
    Abstract: A nitride semiconductor device includes a silicon substrate, a nucleation layer, a first buffer layer, a first type nitride semiconductor layer, a light-emitting layer and a second type nitride semiconductor layer is provided. The nucleation layer is disposed on the silicon substrate. The first buffer layer is disposed on the nucleation layer. The first buffer layer includes a dopant and Gallium, and an atomic radius of the dopant is larger than an atomic radius of Gallium. The first type nitride semiconductor layer is disposed over the first buffer layer. The light-emitting layer is disposed on the first type nitride semiconductor layer. The second type nitride semiconductor layer is disposed on the light-emitting layer.
    Type: Application
    Filed: October 9, 2012
    Publication date: April 10, 2014
    Applicant: Industrial Technology Research Institute
    Inventors: Yen-Hsiang Fang, Chen-Zi Liao, Rong Xuan, Chien-Pin Lu, Yi-Keng Fu, Chih-Wei Hu, Hsun-Chih Liu
  • Publication number: 20140054593
    Abstract: A nitride semiconductor structure is provided. The nitride semiconductor structure at least includes a silicon substrate, a AlN layer, a AlGaN layer and a GaN layer formed on the AlGaN layer. The silicon substrate has a surface tilted at 0<tilted?0.5° with respect to a axis perpendicular to a (111) crystal plane, and the AlN layer is formed on the surface. The AlGaN layer is formed on the AlN layer. Moreover, an Al content in the AlGaN layer is decreased gradually in a layer thickness direction from the silicon substrate side toward the GaN layer side.
    Type: Application
    Filed: August 22, 2012
    Publication date: February 27, 2014
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chen-Zi Liao, Chih-Wei Hu, Yen-Hsiang Fang, Rong Xuan
  • Patent number: 8587017
    Abstract: A light emitting device and a method of fabricating a light emitting device are provided. The light emitting device includes a carrier substrate, at least one epitaxy structure, a high resistant ring wall, a first electrode, and a second electrode. The epitaxy structure is disposed on the carrier substrate and includes a first semiconductor layer, an active layer, and a second semiconductor layer stacked in sequence. The first semiconductor layer is relatively away from the carrier substrate and the second semiconductor layer is relatively close to the carrier substrate. The high resistant ring wall surrounds the epitaxy structure and a width of the high resistant ring wall is greater than 5 ?m. The first electrode is disposed between the carrier substrate and the epitaxy structure. The second electrode is disposed at a side of the epitaxy structure away from the carrier substrate.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: November 19, 2013
    Assignee: Industrial Technology Research Institute
    Inventors: Wei-Hung Kuo, Yi-Keng Fu, Suh-Fang Lin, Rong Xuan