Abstract: A memory transistor comprises a substrate comprising a first surface and a second surface opposing the first surface, the substrate further comprising a first trench having an opening formed in the first surface; a first dielectric layer formed on an inner surface of the first trench; a gate layer formed on the first dielectric layer in the first trench, the gate layer having a top surface lower than the first surface; and a second dielectric layer filled in the first trench and located on the top surface of the gate layer, the second dielectric layer covering the gate layer and connecting to the first dielectric layer, the second dielectric layer having a cavity formed therein.

Abstract: A semiconductor device structure and fabrication method thereof are disclosed. The method may include providing a substrate; forming a gate structure on the substrate; forming a spacer structure on the gate structure, and forming a contacting conductive structure on the spacer structure. The spacer structure may cover a side wall of the gate structure, and may include a first spacer layer having a first dielectric constant and a second spacer layer having a second dielectric constant different from the first dielectric constant. The contacting conductive structure may cover a side wall of the spacer structure that is defined by a first side surface of the first spacer layer and a second side surface of the second space. The ratio of the area of the second side surface of the second spacer layer to the total area of the side wall of the spacer structure may be in a range from 78% to 98%.

Abstract: An asymmetric fin field-effect transistor (FinFET) in a memory device, a method for fabricating the FinFET and a semiconductor device are disclosed. In the provided FinFET and method, each of the active areas comprises a fin, a length of a first end of the fin on a first side of the active area and covered by the word line being different from a length of a second end of the fin on a second side of the active area and covered by the word line. For this reason, the present invention allows reduced process difficulty. In addition, the different lengths of the word lines can induce a weaker unidirectional electric field which suffers from much less current leakage, compared to a bidirectional electric field created in word lines with equal such length.

Abstract: A semiconductor device structure and fabrication method thereof are disclosed. The method may include providing a substrate; forming a gate structure on the substrate; forming a spacer structure on the gate structure, and forming a contacting conductive structure on the spacer structure. The spacer structure may cover a side wall of the gate structure, and may include a first spacer layer having a first dielectric constant and a second spacer layer having a second dielectric constant different from the first dielectric constant. The contacting conductive structure may cover a side wall of the spacer structure that is defined by a first side surface of the first spacer layer and a second side surface of the second space. The ratio of the area of the second side surface of the second spacer layer to the total area of the side wall of the spacer structure may be in a range from 78% to 98%.

Abstract: A semiconductor device structure and fabrication method thereof are disclosed. The method may include providing a substrate; forming a gate structure on the substrate; forming a spacer structure on the gate structure, and forming a contacting conductive structure on the spacer structure. The spacer structure may cover a side wall of the gate structure, and may include a first spacer layer having a first dielectric constant and a second spacer layer having a second dielectric constant different from the first dielectric constant. The contacting conductive structure may cover a side wall of the spacer structure that is defined by a first side surface of the first spacer layer and a second side surface of the second space. The ratio of the area of the second side surface of the second spacer layer to the total area of the side wall of the spacer structure may be in a range from 78% to 98%.

Abstract: A method for forming a capacitor profile on a semiconductor is disclosed. The method includes: providing a semiconductor substrate; forming a dielectric layer on the semiconductor substrate; forming an ion reflecting mask layer on the dielectric layer; forming a plurality of patterned openings by etching through the ion reflecting mask layer to expose the dielectric layer; and forming a plurality of trenching capacitor profiles by etching through the dielectric layer from the plurality of patterned openings, respectively, to expose the semiconductor substrate. Each trenching capacitor profile includes a bowing profile formed at 75%-95% of a height of the trenching capacitor profile above the semiconductor substrate.

Abstract: An asymmetric fin field-effect transistor (FinFET) in a memory device, a method for fabricating the FinFET and a semiconductor device are disclosed. In the provided FinFET and method, each of the active areas comprises a fin, a length of a first end of the fin on a first side of the active area and covered by the word line being different from a length of a second end of the fin on a second side of the active area and covered by the word line. For this reason, the present invention allows reduced process difficulty. In addition, the different lengths of the word lines can induce a weaker unidirectional electric field which suffers from much less current leakage, compared to a bidirectional electric field created in word lines with equal such length.

Abstract: A memory transistor comprises a substrate comprising a first surface and a second surface opposing the first surface, the substrate further comprising a first trench having an opening formed in the first surface; a first dielectric layer formed on an inner surface of the first trench; a gate layer formed on the first dielectric layer in the first trench, the gate layer having a top surface lower than the first surface; and a second dielectric layer filled in the first trench and located on the top surface of the gate layer, the second dielectric layer covering the gate layer and connecting to the first dielectric layer, the second dielectric layer having a cavity formed therein.

Abstract: A method for forming a capacitor profile on a semiconductor is disclosed. The method includes: providing a semiconductor substrate; forming a dielectric layer on the semiconductor substrate; forming an ion reflecting mask layer on the dielectric layer; forming a plurality of patterned openings by etching through the ion reflecting mask layer to expose the dielectric layer; and forming a plurality of trenching capacitor profiles by etching through the dielectric layer from the plurality of patterned openings, respectively, to expose the semiconductor substrate. Each trenching capacitor profile includes a bowing profile formed at 75%-95% of a height of the trenching capacitor profile above the semiconductor substrate.

Abstract: A semiconductor device structure and fabrication method thereof are disclosed. The method may include providing a substrate; forming a gate structure on the substrate; forming a spacer structure on the gate structure, and forming a contacting conductive structure on the spacer structure. The spacer structure may cover a side wall of the gate structure, and may include a first spacer layer having a first dielectric constant and a second spacer layer having a second dielectric constant different from the first dielectric constant. The contacting conductive structure may cover a side wall of the spacer structure that is defined by a first side surface of the first spacer layer and a second side surface of the second space. The ratio of the area of the second side surface of the second spacer layer to the total area of the side wall of the spacer structure may be in a range from 78% to 98%.